Modern mathematical models for automatic analysis of electrical characteristics of integrated circuits are considered. The requirements for the analysis programs are formulated. A comparative analysis of machine methods for calculating integrated circuits is carried out in terms of their accuracy, RAM volumes and calculation time. The features of the development of modern automation tools for designing integrated circuits are considered. One of the main tasks of designing an integrated circuit is a schematic analysis, which must be carried out both at the preliminary stage and after the development of the integrated circuit topology. However, it is possible to identify the main re-quirements that a modern analysis program must meet: reliability - stable calculation of a wide class of electronic circuits, obtaining solutions even for poorly conditioned tasks; high performance - this requirement is especially important when calculating BIS, in tasks of multivariate analysis, such as statistical analysis, and optimization; low costs of machine memory and expansion of the maximum permissible complexity of the analyzed circuits; flexibility, the possibility of making changes to the program, in particular, the replacement of mathematical models of circuit components, the introduction of new models, the improvement of the computational algorithm, the inclusion of the pro-gram in more complex programs, etc.; the availability of convenient input and output of initial information.

The article is devoted to the analysis of the behavior of a mobile robot using finite state machine algorithms in order to find a way to the goal and avoid obstacles. After justifying the use of such methods, the analysis of a standard deterministic finite automaton is done. Further, the theory of Markov processes is applied to this algorithm, as a result of which the state machine becomes part of the hidden Markov model. This allows you to apply probabilistic methods to modeling the behavior of the robot. This probabilistic behavior is most promising in complex environments with unpredictable obstacle configurations. To compare the efficiency of deterministic and probabilistic finite state machine, we applied a genetic algorithm. In the numerical experiment that we conducted in the Scilab software, we considered two main types of environments in which a mobile robot can move - an office-type environment and a polygonal-type environment. For each type of environment, we alternately applied each of the indicated behavior algorithms. For the genetic algorithm, we used one hundred individuals who were trained over 1000 generations to find the most optimal path in the specified environments. As a result, it was found that the deterministic finite state machine algorithm is the most promising for movement in an office-type environment, and the probabilistic finite state machine algorithm gives the best result in a complex polygonal environment.

The technology of modeling a field-effect transistor in the CAD system COMSOL Multiphysics is considered. The possibilities of CAD, its methods of graphical construction of the model and methods of modeling the behavior of the model are being studied. The object of study is the MOS transistor, its scope, operation and a mathematical model that can be used in designing its operation. The Shikhman-Hodges model, input and output parameters are determined, the degree of its adequacy to a real transistor is set, the main parameters are determined, with the help of which it is possible to conduct a study of a field-effect transistor, its current-voltage characteristic. A transistor model is built in the mode of operation in the mode of small-signal amplifiers, replacing it with a linear four-port model, it is described when this model can be applied when simulating the operation of the device.

Definitions are given and the difference between positive and negative algebra of logic is indicated. It is noted that when switching from positive logic to negative, the elements of "Schaeffer's Stroke" and "Pierce's Arrow" change places. Similarly, conjunction changes with disjunction. The inverter retains its property regardless of its application in positive or negative logic. The laws and rules valid for the negative algebra of logic are presented. The method of transition from the positive algebra of logic to the negative one is presented. Elements of positive and negative logic are compared. On the basis of logic functions: (AᴧBᴧC)ᴧDvAᴧ(BᴧCᴧD)vAᴧ(BᴧC)ᴧDv(AᴧB)ᴧ(CᴧD), implemented by direct optimized, minimal, options matching device, as well as, the final options in bases 2-NOT-OR (2-AND-NOT), 4-NOT-OR (4-AND-NOT) for negative logic. The voltage table of K155LE1, K155LE3 microcircuits is presented. The truth table of K155LE1, K155LE3 microcircuits in negative logic algebra (as an element AND-NOT or NOT-OR) is presented. Truth tables of K176LE5, K176LE6 microcircuits are shown in positive logic algebra (OR-NOT). The voltage table of K176LE5, K176LE6 microcircuits is shown. The truth table of K176LE5, K176LE6 microcircuits is shown in negative logic algebra (as an AND-NOT or NOT-OR element). elements of negative logic. Conclusion about the results.

The fundamental laws of the positive algebra of logic are considered, including the rules relating to the elements of equivalence and non-equivalence. Logic gates used in practice are presented. The whole set of standard schemes is implemented, in particular, the frontal version, minimized, in the "OR–NOT" basis, in the "AND–NOT" basis based on the initial logical dependence: ¬(¬(A¬B) × ¬(¬CD) + ¬(¬AB) × ¬(C¬D)) + ¬(¬(AB) × ¬(CD) + ¬(¬A¬B) × ¬(¬C¬D)) . A combination device based on K176LE5 chips has been designed. It is noted that the implementation of this function requires at least 3 chips in the Pier basis, which is not optimal in terms of reliability and weight and size indicators. The transition from the minimized variant to the basis of "Non-Equivalence" + "Conjunction", as well as the basis of "Equivalence" + "Pierce function" is carried out. The results of the search for existing chips that implement the functions "Exclusive OR", "AND", "Exclusive OR–NOT" and "OR-NOT" are presented. 4 groups of chips were found, such as: chips based on logic with emitter coupling (ECL), based on transistor-transistor logic (TTL), based on a series of CMOS chips: with a supply voltage of 5-15 V, and also with a supply voltage of 3-5 V. The corresponding descriptions of each of the MC10H1xx chips (group 1 series); K155xx, xx74xx (group 2 series); K561xx, CD40xxxx (group 3 series); SN74LVCxxx (group 4 series) are presented. Implementation options for these groups of chips in both bases are presented. The cost analysis of the applied microcircuits is made. The calculation of the final cost of products is presented. The conclusion is made about the expediency of using one or another group of microcircuits, depending on the initial requirements set.