during data transfer between processor and memory. [6] To overcome this limitation, various research activities on computing in-memory have been conducted to optimize neural network computations. [7] Especially, numerous non-volatile memory devices have been proposed to update synaptic weights and perform matrix-vector multiplications (MVM). [8] However, most previous artificial synapse devices cannot satisfy all the requirements for high-performance neural network operations, for example, a large number of weight levels, wide conductance range, linear/symmetric weight update, outstanding device-to-device uniformity, low operating power, long retention, and good endurance. Resistive random access memory (RRAM) and phase change memory (PCM) exhibit a wide range of conductance changes, but show nonlinear weight modulation and poor device-todevice uniformity due to the abrupt transitions during device operation. [9][10][11] Spin-transfer torque magnetic random access memory shows extremely low programming delay and power consumption, but its conductance range is limited. [12] Flash memory and ferroelectric field-effect transistor (FeFET) exhibit outstanding CMOS compatibility and a wide conductance range; however, flash memory requires high operation voltage, and FeFET has poor fatigue characteristics, which results in cycle-tocycle variation. [13][14][15] To overcome the limitations of non-volatilememory-based synapse devices, metal-oxide-semiconductor This work presents an analog neuromorphic synapse device consisting of two oxide semiconductor transistors for high-precision neural networks. One of the two transistors controls the synaptic weight by charging or discharging the storage node, which leads to a conductance change in the other transistor. The programmed weight maintains for more than 300 s as electrons in the storage node are well preserved due to the extremely low off current of the oxide transistor. Ideal synaptic behaviors are achieved by utilizing superior properties of oxide transistors such as a high on/off ratio, low off current, and large-area uniformity. To further improve the synaptic performance, self-assembled monolayer treatment is applied for reducing the transistor conductance. The reduction of on current reduces the power consumption, and the reduced off current improves the retention characteristics. There is no noticeable decrease in simulated neural network accuracy even when the measured device-to-device variation is intentionally increased by 200%, indicating the possibility of large-array operation with the synapse device.

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Quantum‐dot‐based a‐IGZO phototransistor has become one of the promising devices for image sensor application due to its bandgap tunability and solution‐process compatibility. However, the QD phototransistor with a‐IGZO, which contains a large amount of charge traps on the surface, exhibited slow photoresponse (τdecay >10 s). In this work, the photocurrent and decay time were significantly enhanced by 2.2 times and 73%, respectively, by introducing a self‐assembled monolayer (SAM), which effectively passivates the traps at the QD/a‐IGZO interface.

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