The effects of impurities such as gold, iron, copper, nickel, tantalum, and tungsten on junction reverse I‐V characteristics were investigated using DLTS (deep level transient spectroscopy), TSCAP (thermally stimulated capacitance), I‐V , C‐V , and I‐T measurements. In almost all cases, the reverse I‐V characteristics consisted of two components; a normal Shockley‐Read‐Hall (SRH) generation component and a soft leakage component which dominates the SRH component above a given onset voltage. Only the SRH component can be detected with the DLTS and TSCAP methods. The soft leakage currents were ascribed to the presence of impurity precipitates lying near the metallurgical junction of the devices. Soft leakage currents measured at 80°K were fitted to a Fowler‐Nordheim field‐emission model. Localized electric field values near the precipitates of the order of 106–107 V/cm were obtained by this analysis. These values could be correlated with the possible shape of the precipitates. The distribution of the SRH generation centers within the active regions of the devices and the activation energies of the emission rates of above‐mentioned impurities were measured using the DLTS technique. The following results were obtained: Au 0.55 eV (c), Fe 0.57 eV (c); Cu 0.2 eV (c), 0.49 eV (v), 0.41 eV (v); Ni 0.19 eV (c), 0.36 eV (c); Ta 0.21 eV (c); and W 0.25 eV (c), 0.28 eV (c), respectively. Here c and vrepresent measurements from the conduction band and valence band, respectively.

A method for precision thhming sihcon integrated circuit shces has been developed whereby either η or ρ type regions may be selectively removed from material of opposite conductivity. The existence of a simple and economical means to attain precise thickness control permits more complete advantage to be taken of many sihcon IC structures. For example, precise thickness control, together with anisotropic* etching of isolation/separation slots, is expected to permit economical fabrication of high component density, air-isolated monolithic' inte grated circuits.This method differs from previous electrochemical techniques' in that unwanted sihcon is removed chemically, while the regions to be retained are passivated electrochemically. Accordingly, etchants are used for which sihcon to be retained is passive when biased above some critical voltage, V"..,, while regions to be removed are at a potential below Vp," .Hot aqueous alkahne solutions form a useful class of etchants for this apphcation, for orientations other than (111). These etchants are characterized by a relatively sharp active/passive transition (V,.,, = Vp." ~ 0.5 volt) and by a large ratio of silicon etch rates between the active and passive states. Ratios of greater than 200 : 1 are readily obtained. The ratio of active etch rate/passive etch rate is very impor tant, because this quantity in part determines the thickness uncertainty.Application of the technique to the formation of thin, uniformly thick η type silicon shces is illustrated in Fig. 1. If ν",,, > Vp." , then V" = V"ii > Vp." and the η region will be retained. If Ve.n is restricted to voltages such that the leakage of the reverse biased junction is 473

The electroless gold plating process developed in this laboratory has been successfully applied to the fabrication of beam leads on silicon integrated circuits. This unique plating process selectively plates gold onto discrete patterned regions of a substrate at 6 ~m/hr with ~10% thickness nonuniformity for thicknesses of 10-12 ~m. Beam lead patterns were formed either

Anisotropic silicon etches which preferentially attack the 100 and 1110) crystal planes have been used to form narrow well-controlled d a t i o n slots in silicon beam-leaded integrated circuits.

Low-and high-barrier Schottky diodes have been combined with bipolar transistors to produce planar integratedcircuit low-area memory cells that hold at 75 ,aW. Low-barrier diodes formed on p-type ion-implanted silicon (10'T cm-') are used as high-resistance collector loads. High-barrier diodes formed on n-type epitaxial silicon (1016 cm-8) provide low-capacitance low-Ieakage coupling to digit lines in a memory array.The highly reproducible rho&lum silicide on s~lcon Schottky diodes, as well as high-quality otilc contacts, are formed in one sequence of sputtering and high-temperature operations. The process is fully compatible with beam-lead technology. It is estimated that a 5K?-word memory module using these cells would operate at a 60-ns READor WRITEcycle time.