There is strong evidence indicating that the particular form used to recast the Einstein equation as a 3 + 1 set of evolution equations has a fundamental impact on the stability properties of numerical evolutions involving black holes and/or neutron stars. Presently, the longest lived evolutions have been obtained using a parametrized hyperbolic system developed by Kidder, Scheel and Teukolsky or a conformal-traceless system introduced by Baumgarte, Shapiro, Shibata and Nakamura. We present a new conformal-traceless system. While this new system has some elements in common with the Baumgarte-Shapiro-Shibata-Nakamura system, it differs in both the type of conformal transformations and how the nonlinear terms involving the extrinsic curvature are handled. We show results from 3D numerical evolutions of a single, non-rotating black hole in which we demonstrate that this new system yields a significant improvement in the lifetime of the simulations.
An uncooled microbolometer image sensor, used in an IR image sensor, is made by a micro electro mechanical systems (MEMS) process, so the value of the microbolometer resistor has a process variation. Also, the reference resistor, which is used to connect to the microbolometer, is fabricated by a standard CMOS process, and the difference between the values of the microbolometer resistor and the reference resistor generates an unwanted output signal for the same input from the sensor array. In order to minimize this problem, a new CMOS read-out integrated circuit (ROIC) was designed. Instead of a single input mode, a differential input mode scheme and a simple method to compensate the resistor value are proposed. Using results from a computer simulation, it is observed that the output characteristic of the ROIC was improved and the effect of the process variation was decreased without using complex compensation circuits. Based on the simulation results, a prototype device including an ROIC that was fabricated by a standard 0.25um CMOS process and a microbolometer with a 16 x 16 sensor array was fabricated and characterized.
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.
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