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A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guarantied by epitaxial process. The SON process allows the buried dielectric (which may be an oxide but also an air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.

Low-temperature epitaxial growth of Si and Si1−xGex (referred to as SiGe, hereafter) has been obtained using an industrial, 200 mm, single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content ⩽30% have been studied for buried channel applications in (PMOSFET) devices or as base for heterojunction bipolar transistors (HBTs). The dependence of Si and SiGe deposition rates on filling ratio and exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. In contrast to selective Si growth where the global loading effect decreases slowly with temperature, the growth rate of SiGe at low temperature is strongly dependent on the oxide coverage. The addition of HCl into the gas mixture allows minimizing the dependence of the SiGe growth rate on both oxide coverage and window size. The effect of the addition of HCl on Ge and dopants incorporation is investigated on bare and/or device wafers. Results on facet formation and orientations are also presented for selective Si and SiGe growths. Finally, we report basic electrical results on selective Si epitaxial and SiGe heteroepitaxial structures, which have been integrated in PMOSFET and HBT devices.

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