This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cellaware (CA) library characterization and patterngeneration flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results from a 32-nm notebook processor to which CA test patterns were applied, including the defect rate reduction in PPM that was achieved after testing 800,000 parts. We also present cell-internal diagnosis and physical failure analysis results from one failing part.

This paper focuses on a new approach to significantly improve the overall defect coverage for CMOS-based designs with the final goal to eliminate any system-level test. This methodology describes the pattern generation flow for detecting cell-internal small-delay defects caused by cell-internal resistive bridges. Results have been evaluated on 1,900 library cells of a 32-nm technology. First production test results are presented from evaluating additional defect detections achieved with different fault models on a 45-nm design.

This paper describes a new approach for quickly ramping up the yield for new CMOS technologies by performing a cell-internal (CI) diagnosis based on the cell-aware (CA) methodology. We present results from carrying out this new method on a test chip of a 28-nm technology. After creating defect-oriented CA test patterns for this test chip, we tested various wafers with those CA patterns, selected fail data, conducted a normal electrical failure analysis, and used the new CI diagnosis method to guide the physical failure analysis (PFA) process to look specifically for hot-spot areas within standard library cells. This new approach can reduce the yield ramp-up time significantly.