No abstract

No abstract

The present experimental and computational study investigates a new exhaust gas waste heat recovery system for hybrid vehicles, using a thermoelectric module (TEM) and heat pipes to produce electric power. It proposes a new thermoelectric generation (TEG) system, working with heat pipes to produce electricity from a limited hot surface area. The current TEG system is directly connected to the exhaust pipe, and the amount of electricity generated by the TEMs is directly proportional to their heated area. Current exhaust pipes fail to offer a sufficiently large hot surface area for the high-efficiency waste heat recovery required. To overcome this, a new TEG system has been designed to have an enlarged hot surface area by the addition of ten heat pipes, which act as highly efficient heat transfer devices and can transmit the heat to many TEMs. As designed, this new waste heat recovery system produces a maximum 350 W when the hot exhaust gas heats the evaporator surface of the heat pipe to 170°C; this promises great possibilities for application of this technology in future energy-efficient hybrid vehicles.

In this study, we examine the electrical characteristics of complementary metal-oxide-semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.

Articles you may be interested inComparison of two surface preparations used in the homoepitaxial growth of silicon films by plasma enhanced chemical vapor deposition J. Vac. Sci. Technol. B 21, 970 (2003); 10.1116/1.1568352 Effect of Si cap layer on parasitic channel operation in Si/SiGe metal-oxide-semiconductor structures J. Appl. Phys. 93, 3545 (2003); 10.1063/1.1542916Two-dimensional dopant concentration profiles from ultrashallow junction metal-oxide-semiconductor field-effect transistors using the etch/transmission electron microscopy methodThe loss of the dopant in ultrashallow junction ͑USJ͒ by RCA standard clean ͑SC1͒ prior to the formation of side-wall spacer is quantified by using transmission electron microscopy ͑TEM͒, secondary ion mass spectroscopy, four-point probe, and source/drain extension ͑SDE͒ sheet-resistance test structure ͑SSTS͒. From the cross-sectional TEM images, the etched depth by one SC1 for n ͑p͒-type SDE was measured to be 1.5 nm ͑0.2 nm͒. From the secondary ion mass spectroscopy profiles, most of the n-type dopant implanted with arsenic at 2 keV is expected to be etched-out by four times of SC1 cleaning, while the p-type dopants are immune to SC1 cleaning. We quantified the dopant loss from sheet resistance measurements with the four-point probe and the SSTS. The effect of SC1 cleaning on transistor performance is discussed in terms of on-state current. The dopant loss by SC1 is found to be the most significant factor in process optimization for n-type field effect transistor with USJ.