We have studied the strain state, film and surface morphology of SiGe virtual substrates grown by gas-source molecular beam epitaxy (use of disilane and germane). The macroscopic strain relaxation and the Ge composition of these virtual substrates have been estimated in high resolution x-ray diffraction, using either omega-2 theta scans or reciprocal space maps around the (004) and (224) orders. Typically, linearly graded Si 0.67 Ge 0.33 virtual substrates 2.5 µm thick are 97% relaxed. From transmission electron microscopy, we confirm that the misfit dislocations generated to relax the lattice mismatch between Si and SiGe are mostly confined inside the graded layer. The surface roughness of the relaxed SiGe virtual substrates increases significantly as the Ge concentration and/or the growth temperature exceeds 20%/600 • C. At 550 • C, we find for the technologically important Ge concentration of 30% a surface root mean square roughness of 12 nm, with an undulation wavelength for the cross-hatch of the order of one micron.

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The performance of surface channel MOSFET devices depends on the Si/SiO 2 interface quality. The present study has examined the Si/SiO 2 interface of strained Si n-channel MOSFETs fabricated on a Si/SiGe virtual substrate. Evidence of a variation in the oxidation rate of strained Si along the cross-hatch period is presented. The undulating oxide thickness was found to be accompanied by increased nanoscale roughness at the Si/SiO 2 interface for the strained Si surface channel devices compared with conventional MOSFETs. Fluctuations in the strained Si surface channel thickness were additionally caused by the variation in oxidation rate. The control devices exhibited a tighter distribution of electrical characteristics than the strained Si devices due to the non-uniform cross-hatch severity across the Si/SiGe wafer. The results provide strong evidence that significantly enhanced performance of HNMOS surface channel devices is possible through optimization of epitaxial growth methods. Strain in the channel was maintained following device fabrication using a conventional process with a reduced thermal budget.