Purpose -The purpose of this paper is to design and realize a high gain power amplifier (PA) with low output back-off power using the InGaP/GaAs HBT process for WCDMA applications from 1.85 to 1.91 GHz. Design/methodology/approach -A three stages cascaded PA is designed which observes a high power gain. A 100 mA of quiescent current helps the PA to operate efficiently. The final stage device dimension has been selected diligently in order to deliver a high output power. The inter-stage match between the driver and main stage has been designed to provide maximum power transfer. The output matching network is constructed to deliver a high linear output power which meets the WCDMA adjacent channel leakage ratio (ACLR) requirement of 2 33 dBc close to the 1 dB gain compression point. Findings -With the cascaded topology, a maximum 31.3 dB of gain is achieved at 1.9 GHz. S11 of less than 2 18 dB is achieved across the operating frequency band. The maximum output power is indicated to be 32.7 dBm. An ACLR of 2 33 dBc is achieved at maximum linear output power of 31 dBm. Practical implications -The designed PA is an excellent candidate to be employed in the WCDMA transmitter chain without the aid of additional driver amplifier and linearization circuits. Originality/value -In this work, a fully integrated GaAs HBT PA has been implemented which is capable to operate linearly close to its 1 dB gain compression point.

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This paper describes a 3.5-GHz up-conversion mixer core utilized in a two-step transmitter architecture in compliance with IEEE 802.11a WLAN application. The architecture is based on current-draining folded architecture and is implemented in 0.18-µm CMOS technology, which alleviates the need of bulky resonator integration. The main advantages of the introduced mixer topology are high linearity and high isolation. The low-voltage architecture consumes 5.17 mA of current from 1.8-V supply and shows -2.09-dBm IIP 3 and -9.82-dBm IP 1dB . The proposed architecture observes an output power of -43.69 dBm at the up-converted 3.7 GHz sideband, with -30 dBm and -10 dBm of input baseband and local oscillator power, respectively.

A thermal response model for designing thermal energy storage heatsink utilized for electronics cooling is developed in this paper. In this study, thermal energy storage (TES) heatsink made out of aluminum with paraffin as the phase change material (PCM) is considered. By using numerical simulation, stabilization time and maximum operating temperature to transition temperature difference is obtained for varying fin thicknesses, fin height, number of fins and PCM volume. The numerical simulation results were then compared with existing experimental work. The numerical results matched the melting temperature variation obtained by the experimental work. The validated numerical results are then used to train the artificial neural networks (ANN) to predict stabilization time and maximum operating temperature to transition temperature difference for new fin thicknesses, fin height, number of fins and PCM volume. Finally the optimization of the fin thickness, fin height, number of fins and PCM volume of the thermal energy storage heatsink is obtained by embedding the trained ANN as a fitness function into genetic algorithms (GA). The objective of optimization is to maximize stabilization time and to minimize maximum operating temperature to transition temperature difference. Finally the optimized results for the TES heatsink is used to build a new computer model for numerical analysis. The final optimized model results and the validated preliminary model results are then compared. The final results will show a significant improvement from the validated model. Further the study will show that by combining ANN and GA, a superior tool for optimization is realized.

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