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In this work, we present the results of threedimensional CMOS image sensor cell simulation. Electrical characteristics of the device are represented comprehensively.The methodology, describing saturation, charge-voltage conversion, and image lag of a CIS cell in a single simulation analysis, is expected to play a key role in future CMOS image sensor cell development.

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Silicon-on-Insulator (SOI) CMOS technology has proven to be compatible with bulk CMOS in many ways, ranging from circuit design, layout to wafer processing [l]. In addition, the Partially-Depleted (PD) SO1 technology has been suggested as a method for achieving a high circuit performance at low supply voltage and low power [21. Unlike Fully-Depleted (FD) SO1 transistors, PD SO1 devices have the advantage of a threshold voltage VT which is insensitive to variations in the uniformity of the silicon thickness. This is illustrated in Fig. l(a), which represents the simulated VT as function of the silicon thickness tsi for several (uniform) channel doping levels. Based on device physics, Fig. 1 clearly shows that the long-channel threshold voltage VT is equal to the VT of the bulk transistor as long as the channel doping concentrations are equal.Therefore, the design of a PD SO1 CMOS technology appears to be ve'y similar to conventional bulk. Often, the design of a PD SO1 CMOS technology is started from a present and well-known baseline bulk CMOS technology [2]. During device fabrication, it is assumed, however, that the diffusivity of the channel dopants in the vertical direction in SO1 is similar to bulk, which is fundamentally incorrect. This follows, for example, from the measured doping concentration profiles presented in Fig. l(b). Indium has been implanted as a channel dopant in both an SO1 (tsi=175 nm) and bulk wafer with an energy and dose of 200 keV and 1.0x1O"/cm2, respectively. The presented spectra have been measured after full device fabrication, including several thermal treatments. From Fig. l(b), it is clear that the diffusion behaviour of the indium channel dopants in an SO1 structure is basically different from bulk. Since, the SO1 structure is symmetrical in the sense that it contains two Si/Si02 interfaces instead of only one in the bulk case, the peak concentration of the 'as implanted' indium profile (not shown) has shifted much less towards the front Si/Si02 interface. Consequently, this will result in a shift in the long-channel threshold voltage VT.In order to investigate the threshold voltage VT difference between PD SO1 and bulk, SO1 CMOS transistors have been fabricated on BESOI wafers with a buried oxide and silicon layer thickness of 350 and 125 nm, respectively. In order to obtain a straight comparison with the bulk CMOS technology, each SO1 wafer has a bulk counterpart for which the process conditions have been exactly the same. In the nMOS transistors, boron or indium has been used as a channel dopant, while arsenic or antimony has been used for the PMOS devices. Figures 2 and 3 show the comparison between the threshold voltage VT of the SO1 and bulk transistors. The VT characteristics for boron, presented in Fig. 2(a), show a Reverse Short-Channel Effect (RSCE) for both PD SO1 and bulk devices [3], while an Enhanced Short-Channel Effect (ESCE) is observed for the indium transistors. This behaviour is typical for indium [4]- [5]. The long-channel V, difference between SO1 and bulk is ...