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We report in this paper the fabrication and characterization of a new gate-planarized organic polymer thin-film transistor (GP OP-TFT). We describe in detail the effects of the measurement procedure on the GP OP-TFT electrical characteristics and extracted parameters and show that it is extremely critical to carefully control the electrical measurement conditions to obtain accurate and meaningful results, before any material optimization is undertaken. We also describe the importance of normalization of electrical characteristics and extracted parameters for a proper comparison of different devices. Finally, we report and analyze the gate voltage and channel length dependence of the TFT field-effect mobility.

High-performance top-gate hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structures have been fabricated over a large area from plasma-enhanced chemical vapor deposition (PECVD) materials. The electrical performances of the top-gate a-Si:H TFT (µ FE ≈ ≈0.75cm 2 /Vsec, V T ≈ ≈3.5V, S≈ ≈0.55V/dec) are comparable to the electrical performances observed for an inverted-staggered bottom-gate a-Si:H TFT. We have shown that the TFT field-effect mobility first increases with the a-Si:H thickness, and then decreases for thicker a-Si:H films. This change of the electrical performances can be associated either with the variation of a-Si:H microstructure with film thickness during the PECVD processes or a large density of TFT back interface states; it also involves the source/drain parasitic access resistances, especially for thick a-Si:H layers.

A new hydrogenated amorphous silicon (a-Si:H) thirl film transistor (TFT) structure containing an extra field plax under the gate electrode is proposed. In this a-Si:H TF r, even at the high drain-to-source (VDs) and gate-tosoL:ie (VGS) voltages, a low OFF-current and a high ON'OFF-current ratio can be achieved by alleviating a high electric field at the drain electrode edge. It is expected that this a-Si:H TFT structure can be used for active-matrix reflective cholesteric liquid-crystal displays that require high data and gate driving voltages.