An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

Carbon nanotube (CNT)-based electronics are a potential candidate to replace silicon complementary metal-oxide-semiconductor (CMOS) technology, which will soon meet its performance limit at the 7 or 5 nm technology node 1,2 . Prototype device studies using individual CNTs have shown that nanotube electronics have the potential to outperform Si CMOS technology in both performance and power consumption [3][4][5][6] , and are even close to the theoretical limits for all field-effect-transistor(FET)-based binary switches 7,8 . Recently, FETs were fabricated using aligned CNT arrays, and shown to have a higher channel conductance (at a lower bias) than that of Si CMOS FETs 9 . However, the key performance metrics reported for such CNT FETs, including on-state current density (I on ) and transconductance (g m ), are still substantially lower than those of conventional Si CMOS FETs at the same characteristic length [9][10][11][12][13] . The ideal material system for high-performance CNT electronics has been identified as a parallel array film of intrinsic pure semiconductor single-walled nanotubes of a single chirality with a diameter of approximately 1.3 nm and no defects, and a tube-tube spacing of 5-8 nm (ref. 14 ). Although such an ideal material system is yet to be realized, many breakthroughs in the purification and controlled synthesis of CNTs have been made in recent years [15][16][17][18][19] , suggesting the possibility of achieving the required nanotube purity and array density before 2020 14 . Using randomly oriented or aligned CNT array films, various types of CNT thin-film FETs have been fabricated [9][10][11][12][13] . However, hindered by the limited performance of nanotube FETs, the operation speed of CNT integrated circuits (ICs) 20-31 typically falls short of their expected terahertz potential, and that achieved by Si CMOS circuits (gigahertz), by several orders of magnitude. Notably, CNT-based ring oscillators (ROs) with an oscillation frequency (f o ) of 282 MHz have recently been reported 32 . However, CNT-thin-film-based ICs typically have a working frequency of less than 1 MHz, which might be useful for flexible electronics, but is not suitable for mainstream high-performance CMOS technology 33 . In this study, we used a randomly oriented CNT film to build CNT FETs and ICs, fabricating, in particular, five-stage ROs with f o of up to 5.54 GHz. The random CNT film is essentially the same as a network film, but here we used the term 'random film' to emphasize that our FETs are contact dominated and have a different transport mechanism to that of junction-dominated network-type FETs 34,35 . In principle, aligned CNT arrays would provide better device performance, but it remains a challenge to obtain wafer-scale aligned CNT arrays with high uniformity, high density and high semiconductor purity for constructing high-performance ICs. Although it is not the ideal scheme, the FET-and IC-based random CNT film can nevertheless provide a feasible demonstration to assess the floor-level performance (f...

Semiconducting single-walled carbon nanotubes (s-SWNTs) with diameters of 1.0-1.5 nm (with similar bandgap to crystalline silicon) are highly desired for nanoelectronics. Up to date, the highest reported content of s-SWNTs as-grown is ∼97%, which is still far below the daunting requirements of high-end applications. Herein, we report a feasible and green pathway to use HO vapor to modulate the structure of the intermetallic WCo nanocrystals. By using the resultant WCo nanocatalysts with a high percentage of (1 0 10) planes as structural templates, we realized the direct growth of s-SWNT with the purity of ∼99%, in which ∼97% is (14,4) tubes (diameter 1.29 nm). HO can also act as an environmentally friendly and facile etchant for eliminating metallic SWNTs, and the content of s-SWNTs was further improved to 99.8% and (14,4) tubes to 98.6%. High purity s-SWNTs with even bandgap determined by their uniform structure can be used for the exquisite applications in different fields.

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Although chemical vapor deposition (CVD)-grown carbon nanotube (CNT) arrays are considered ideal materials for constructing high-performance field-effect transistors (FETs) and integrated circuits (ICs), a significant gap remains between the required and achieved densities and purities of CNT arrays. Here, we develop a directional shrinking transfer method to realize up to 10-fold density amplification of CNT array films without introducing detectable damage or defects. In addition, the method improves the film uniformity while retaining the perfect alignment and high carrier mobility of 1600 cm V s of CVD-grown CNT arrays. By combining the density amplification method with the thermocapillary flow method developed by Rogers et al., semiconducting CNT arrays with high densities and high qualities are obtained. High-performance FETs with a channel length of 200 nm are demonstrated using these high-density semiconducting CNT arrays, yielding a record-high on-state current density of 150 μA/μm, a peak transconductance of 80 μS/μm, and a current on/off ratio of more than 10 among the CVD-grown CNT-based FETs.