The physical unclonable function (PUF) is a promising low-cost hardware security primitive. Recent advances in nanotechnology have provided new opportunities for nanoscale PUF circuits. The resistive random access memory (RRAM) is extensively used in nanoscale circuits due to its low cost, non-volatility and easy integration with CMOS. This paper proposes a novel tristate hybrid PUF (TH-PUF) design based on a one-transistor-one-RRAM (1T1R) cell; this cell can be configured into two weak PUFs and a strong PUF using few control signals. To assess the proposed PUF design, a compact RRAM model at UMC 65nm technology is employed. Simulation results show that the proposed TH-PUF achieves good uniqueness, reliability as well as a higher gate usability compared with an entire CMOS PUFs. The number of challenge response pairs (CRPs) of the proposed TH-PUF is larger than other RRAM-based PUFs. Moreover, the TH-PUF is more resistant to a modeling machine learning attack than traditional PUF designs.

Compared to traditional ring oscillator PUF (RO PUF), configurable RO PUF (CRO PUF) greatly increases the number of challenge response pairs (CRPs) and improves hardware utilization. However, in the conventional CRO PUF design, when a path is selected by the challenge to generate a response, the circuit characteristic information constituting the CRO PUF, such as the delay information of the configurable unit, the transmission model, and etc., can also be leaked. Once the adversary monitors and masters this information, they can use this information to attack the CRO PUF circuits, such as modeling attacks. This paper establishes a theoretical model of CRO PUF and analyzes its unpredictability and security. Based on this model, a new mechanism to generate the proper challenges is proposed in this paper. In the proposed mechanism, the challenge is generated and utilized by a specific way, which can delay the feature leakage of the CRO PUF, thereby improving the security of the CRO PUF.

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A resistive random access memory (RRAM) as an emerging nanoelectronic device, is widely used for memory and physical unclonable function (PUF) applications. The compatibility of RRAM PUFs with memory architectures can be exploited to reduce the hardware overhead. Therefore, an intrinsic PUF using dynamic variations of resistive crossbar arrays is presented in this paper. Based on an improved sense amplifier (SA), the proposed intrinsic RRAM PUF can be fully configured as a memory cell or a PUF cell, leading to a minimal design overhead. Using the device-to-device (D2D) variation of an RRAM, a significant number of challenge-response pairs (CRPs) is generated with a flexible configuration of the resistive crossbar arrays. The proposed RRAM PUF can be refreshed to a new instance relying on the cycle-to-cycle (C2C) variation of an RRAM. An efficient challenge generation method is presented to improve the security of the proposed RRAM PUF. To verify the performance of the proposed RRAM PUF, 20 instances are simulated and implemented using a compact Spice model and a UMC 65nm CMOS process technology, respectively. The simulation results show that the proposed RRAM PUF exhibits good performances with a high uniqueness, reliability, and reconfigurability. The randomness of the PUF is evaluated by the National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) tests. Moreover, the experimental results show that the proposed RRAM PUF achieves a good resistance against machine learning (ML) attacks.