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The room temperature-operation of a single-electron metal-oxide-semiconductor (MOS) memory with a defined quantum dot fabricated by sidewall patterning technique based on conventional VLSI technologies has been demonstrated without the aid of electron beam (EB) lithography for the first time. Sidewall patterning technique shows a good uniformity and controllability as well as high throughput. The fabricated memory devices show quantized threshold voltage shifts at room temperature. Timedependant measurement of drain current shows discrete electron injection to the quantum dot. In addition, fabricated devices have good subthreshold swing and retention characteristics.

To investigate the substrate current characteristics of a recessed channel structure with graded channel doping profile, we have fabricated and simulated the Inverted-Sidewall Recessed-Channel (ISRC) nMOSFET and compared it with a conventional planar nMOSFET. Experimentally, the ISRC nMOSFET shows about 30% reduction of substrate current, even though the drain current is almost the same. At 0.12-m channel length, the ISUB=IDS value of the conventional nMOSFET is measured to be 1.68 times higher than that of the ISRC nMOSFET. Also, using simulation, it is verified that the reduction of electric field at the drain junction of ISRC nMOSFET results from the graded channel doping profile, not from the recessed channel structure.

We have developed a patterning technique to define ultrafine lines with high density and good uniformity using sidewall structures. Approximately 50 nm multiple lines, which have 70 nm as the narrowest space between the lines, are defined by the pattern multiplication technique. Linewidths are measured at several points on wafers and their uniformity is verified. These patterns have a good uniformity ͑deviation 2.26 -4.35 nm͒. Also, die-to-die uniformity is very good. The advantage of this technique is the easy control ͑using sidewall width control͒ of the line and space of patterns. This technique is free from the proximity effect because of the process using a sidewall hard mask. Thus, it is expected that the pattern multiplication technique can be applied to fabricate single electron devices, quantum devices, and other nanoscale devices.