Spin-transfer torque magnetic random access memory (STT-MRAM) is considered one of the most promising non-volatile memory candidates thanks to its excellent performance in terms of access speed, endurance, and compatibility to CMOS. However, high power supply voltage is required in the conventional STT-MRAM writing circuit, which results in high power consumption (e.g.,∼10 pJ/bit). In addition, it suffers from stochastic switching behavior and process voltage temperature variations. These make power-efficient and reliable write/read circuits become critical challenges. In this paper, we present novel circuits and architectures to build a 16 kb STT-MRAM design with low power and high reliability. For example, the self-enable switching scheme reduces the power consumption effectively and the fore-placed sense amplifier improves the robustness to process variation. Using an accurate compact model of 65 nm STT-MRAM and a commercial CMOS design kit, mixed transient and statistical simulations have been performed to validate this design.

By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.

No abstract

Radiation-induced current gain and noise degradations in NPN bipolar junction transistors are due to accumulation of oxide-trapped charges and interface states at the surface of the device. Based on an available model of base surface current of NPN bipolar junction transistors, a simplified model is presented with some approximations at low total dose level, which can explain the degradation mechanisms of the current gain. Based on the theory of carrier number fluctuation and the simplified model of base surface current, a noise model is developed, which can be used to explain the noise degradation induced by the radiation at low total dose level. The model suggests that the gain and noise degradations can be attributed to the same physical origin, and these two kinds of degradations are the result of accumulation of oxide-trapped charges and interface states. The radiations were performed in a source at a dose rate of 10 rad(Si)/s up to a total dose of 70 krad(Si). The degradations of the current gain and noise are compared, and the relationship between noise and the current gain is given, which accords well with the experimental results. Compared to the current gain, the noise parameter is more sensitive, so it may be used to evaluate the radiation resistance capability of bipolar junction transistors.

A high-performance single-pole single-throw (SPST) RF switch for mobile phone RF front-end modules (FEMs) was designed and characterized in a 0.13 μm partially depleted silicon-on-insulator (PD SOI) process. In this paper, the traditional series-shunt configuration design was improved by introducing a suitably large DC bias resistor and leakage-preventing PMOS, together with the floating body technique. The performance of the RF switch is greatly improved. Furthermore, a new Ron × Coff testing method is also proposed. The size of this SPST RF switch is 0.2 mm2. This switch can be widely used for present 4G and forthcoming 5G mobile phone FEMs.