Wafer bonding became during past decade an important technology for MEMS manufacturing and waferlevel 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.

Metal bonding layers are used in various wafer bonding applications in MEMS and more recent in wafer-level 3D integration and optoelectronics. The bond process investigated in this paper is thermocompression. The most used metals for such applications are Cu, Au and Al, each of them with specific requirements for the wafer bonding process. While Au use doesn't face the problem of surface oxidation, both Cu and Al surfaces are covered by native oxides when exposed to ambient atmosphere: the oxidized surfaces impact on bonding process results, so their condition is crucial for successful process. The main process conditions for Cu-Cu and Al-Al bonding are reviewed and examples are presented.

wafer stacking technologies offer new possibilities in terms of device architecture and miniaturization [1][2][3]. To stack wafers, reliable throughsilicon vias (TSVs) and interconnections must be processed into ultrathin wafers, and such processing is made possible by new methods for wafer handling. Of the different wafer-level bonding techniques, temporary wafer bonding adhesives can offer a variety of properties sufficient for withstanding the TSV processes: flow properties, mechanical strength, thermal stability, chemical resistance, and easy debonding and cleaning processes. This paper demonstrates that, contrary to tapes and waxes currently used for temporary bonding, a new removable high-temperature adhesive  meets all the requirements named above for reliable TSV processing on 8-inch active wafers. We will first describe formation of TSVs with aspect ratios of 1:1 and 2:1 into thinned wafers. IntroductionTo be successful, 3-D ultrathin wafer stacking technologies require the development of reliable through-die interconnects with varying aspect ratios depending on the application. This type of integration poses forward new challenges in the development of new TSV processes suitable for thin-wafer handling technologies.It has already been demonstrated in a previous publication [4] that a temporary bonding process using new hightemperature adhesives  could provide an innovative and robust solution to produce functional 1:1 aspect ratio TSVs in 70-micron-thick silicon wafers. This first result showed that in addition to presenting sufficient thermal and mechanical properties to withstand all the backside process steps, the high-temperature adhesive enables easy bonding, debonding, and cleaning processes.Although encouraging, these first results obtained on plain silicon wafers were not completely representative of TSV integration in industrial products. Indeed, due to the presence of several metallization and passivation layers, an active CMOS-containing wafer can present a different deformation behavior compared to a plain wafer when heated, which can weaken its adhesion to the temporary layer during the process. Therefore the purpose of this paper is to assess the TSV creation on temporarily bonded complex active wafers.In the first part of this paper, we will assess the full TSV realization on device wafers thinned to 70 microns thanks to a temporary bonding process. The active wafers used were

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