The paper discuss the design of 1-bit full adder circuit using Shannon theorem. This proposed full adder circuit is used as one of the circuit component for implementation of Non- Restoring and Restoring divider circuits. The proposed adder and divider schematics are designed by using DSCH2 CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool. The divider circuits are designed by using standard CMOS 0.35 microm feature size and corresponding power supply 3.5 V. The parameters analyses are carried out by BSIM 4 analysis. We have compared the simulated results of the Shannon based divider circuit with CPL and CMOS adder cell based divider circuits. We have further compared the results with published results and observed that the proposed adder cell based divider circuit dissipates lower power, gives faster response, lower latency, low EPI and high throughput.

No abstract

In the conventional second order, single bit, discrete ΔΣ Modulator (DSM), the sampling of input signal and DSM operation is performed at the same frequency. In this conventional DSM, signal to noise ratio (SNR) starts falling down rapidly when the modulus of normalized input signal is above 0.47. The integrators output become arbitrarily large which make the system unstable by saturating the operational amplifiers used in the circuit. There are recent papers in which the modulus of normalized input signal can be increased up to 0.7. In the present paper, a second order DSM with different sampling frequency and DSM clock frequency is proposed. The operating period of the proposed DSM is proportional to the sampled analog input signal. The proposed DSM can operate for the full range of normalized input signal (−1 to +1), has better signal to noise ratio (SNR) in the higher range and can be realized using cmos circuit of supply voltage ²1.5 V. The maximum bound on the integrators outputs is 1.5 V. The proposed DSM has unidirectional output and the oscillation at the output for zero input is no longer present and these properties are essential to drive stepper motors which are the actuators for control valves in industry. In the output spectrum near the signal frequency, the noise level is well below the signal level. The proposed DSM results in low power, stable full range operation with better SNR and power spectral density (PSD).

No abstract

No abstract