The flicker noise characteristics of strained-Si nMOS-FETs are significantly dependent on the gate oxide formation. At high temperature (900 C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700 C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.

A novel layout design for process monitoring test structure of RF MOSFET has been proposed in this paper. The test structure consumes only 62% area of the conventional structure and can be easily inserted into the scribe-line of individual chips. The proposed structure is very suitable for inprocess electrical testing including DC, CV, and RF characterization. And this new layout test structure also can be extended to other DUT measurements, for example, capacitor, diode, varactor, and interconnects.

No abstract

No abstract