We present and discuss a novel dopant control technique for compound semiconductors, called site-competition epitaxy, which enables a much wider range of reproducible doping control and affords much higher and lower epilayer doping concentrations than was previously possible. Site-competition epitaxy is presented for the chemical vapor deposition of 6H-SiC epilayers on commercially available (0001)SiC silicon-face substrates. Results from utilizing site-competition epitaxy include the production of degenerately doped SiC epilayers for ohmic-as-deposited (i.e., unannealed) metal contacts as well as very low doped epilayers for electronic devices exhibiting SiC record-breaking reverse voltages of 300 and 2000 V for 3C- and 6H-SiC p-n junction diodes, respectively.

It is believed that atomic-scale surface steps cause defects in single-crystal films grown heteroepitaxially on SiC substrates. A method is described whereby surface steps can be grown out of existence on arrays of device-size mesas on commercial “on-axis” SiC wafers. Step-free mesas with dimensions up to 200 μm square have been produced on 4H-SiC wafers and up to 50 μm square on a 6H-SiC wafer. A limiting factor in scaling up the size and yield of the step-free mesas is the density of screw dislocations in the SiC wafers. The fundamental significance of this work is that it demonstrates that two-dimensional nucleation of SiC can be suppressed while carrying out step-flow growth on (0001)SiC. The application of this method should enable the realization of improved heteroepitaxially-grown SiC and GaN device structures.

Morphological and electrical characterization results are presented for cubic SiC films grown by chemical vapor deposition on single-crystal Si substrates. The films, up to 40 ~m thick, were characterized by optical microscopy, scanning electron microscopy (SEM), transmission electron microscopy (TEM), electron channeling, surface profilometry, and Hail measurements. A variety of morphological features observed on the SiC films are described. Electrical measurements showed a decrease in the electron mobility with increasing electron carrier concentration, similar to that observed in St. Room temperature electron mobilities up to 520 cm2/V-s (at an electron carrier concentration of 5 • 10 TM cm -~) were measured. Finally, a number of parameters believed to be important in the growth process were investigated and some discussion is given of their possible effects on the film characteristics.

Both 3C-SiC and 6H-SiC single-crystal films can be grown on vicinal (0001) 6H-SiC wafers. We have found that oxidation can be a powerful diagnostic process for (1) ‘‘color mapping’’ the 3C and 6H regions of these films, (2) decorating stacking faults in the films, (3) enhancing the decoration of double positioning boundaries, and (4) decorating polishing damage. Contrary to previously published oxidation results, proper oxidation conditions can yield interference colors that provide a definitive map of the polytype distribution for both the Si face and C face of SiC films. Defects were more effectively decorated by oxidation on the Si face than on the C face.