This paper presents an etch technique capable of three-dimensional (3D) design control for microfluidic channels via reactive ion etching (RIE) lag effects. Predictable results are achieved by the development of a complex Langmuir model relating the exposed surface geometry to the depth and width of microfabricated channels that result after isotropic etching of silicon. The model captures the increase in isotropic etch rate as the amount of the exposed surface area increases. The technique is based on the most complex surface pattern to date, composed of five independent geometric variables. Data from over 350 different patterns and four different etch times were collected to examine the influence of each parameter on the result. This technique provides the capability for vast networks of microcapillary channels and large, low aspect ratio cavities to be created on the same wafer requiring a single SF 6 etch step. Designs utilizing this technique can be realized with 10% accuracy to the models; the main source of inaccuracy arises from wafer-to-wafer process differences. Several microfluidic devices were fabricated, proving the possibility of accurate design, and providing insight into structures achievable from 3D control of microfluidic structures.

This paper presents a new fabrication technique capable of creating three-dimensional (3D) buried microchannels in a silicon substrate. With a single mask and a single etch of the substrate, silicon microstructures are created with control in all three dimensions by utilizing reactive ion etch (RIE) lag. The microstructures are then sealed with plasma enhanced chemical vapor deposition (PECVD) dielectrics. By depositing up to 6.3 μm of PECVD oxide, rectangular openings in the masking layer ranging in size from 2 μm × 2 μm to 4 μm × 10 μm microchannels were sealed. Using these mask openings, microchannels were created with depths ranging from 4 μm to 200 μm. In addition channels with controlled transition between depths and transition slopes ranging from 40 • and 60 • were created. Furthermore, the flexibility of this technique allows for the creation of predictable nano-scaled holes on the substrate surface. The entire process is fabricated on silicon and CMOS compatible, thus allowing for 3D buried channel devices to be integrated with microelectronics. To show the impact of this technique, practical microfluidic devices with a wide range of applications are demonstrated.

No abstract