No abstract

No abstract

No abstract

Microelectronics devices continue to evolve towards increased functionality, thinner die, increased reliability, and reduced cost, requiring a change in material and process requirements for the next generation of packages (i.e. stacked chip packages and wafer level packages (WLP)). Stress reduction is a key factor for many devices, particularly those that have thinner die and those that are subjected to stresses generated by thermal cycling. Wafer level packaging is an area where low stress and high volume manufacturing are critical for achieving good reliability and low manufacturing cost. Dow Coming and IMEC have been investigating a Silicone Under the Bump (SUB) wafer level package as a potential route towards increased reliability. Including a SUB design into the device architecture provides a route to dissipate the stresses generated by the thermal expansion mismatch between the silicon die and the printed circuit board. Key to the device build is the application of a silicone pad using a photosensitive silicone or a screen printable silicone. In the design, metal traces from the bonding pads are redistributed to the tops of the silicone pads. Solder balls are placed on the metallized pads to complete the interconnection. The elastomeric nature of the pad dissipates the stresses created by the mismatch in CTE between the chip and the PCB and extends device reliability.To build the SUB enabled WLP device it was critical to understand the impact of the new materials on the device process steps. The uniqueness of the material set requires the creation and optimization of plasma cleaning processes specific to silicones, direct-on-silicone metallization and metal etching in the presence of silicones. The application of a solder mask and solder ball placement is required to complete a successful device build.In this paper we will discuss in detail the process steps utilized in building a silicone containing WLP. This will include a discussion on the process challenges including silicone pad integration, metallization, solder mask application and solder ball placement. The methodologies described in this paper can be generally applied for integration of photopatternable silicones into a range of devices and packages.

We have evaluated a new Ag-filled silicone thermal interface material (TIM) for its sensitivity to lid finish and impact on imaging discontinuities in the die/lid (TIM1) layer, in conjunction with two high performance lid materials, as a part of our advanced packaging technology development effort. Thermal and mechanical (shear stress and lid pull) measurements have been carried out on a number of different lid finishes to optimize thermal performance and adhesion at the TIM1/lid interface. This silicone TIM1 is found to be sensitive to the type of Ni-plating and plating bath chemistry. Nondestructive and destructive metrology has been carried out on flip chip (FC) packages using Ag-filled silicone TIM1 and either Cu or AlSiC lids. A number of silicone formulations have been investigated to assess their impact on surface acoustic microscopy (SAM) and X-ray imaging. Nondestructive evaluation (NDE) by real time X-ray and SAM has identified artifacts that make it difficult to unambiguously detect voids and delamination in the TIM1 layer. A “dark ring” or “picture frame” artifact is observed at the die perimeter in acoustic microscope images of packages with the Ag-filled TIM1. Detailed SEM cross-section and thermal mapping analyses on a number of specially constructed FC packages have been correlated with TIM1/lid delamination and voiding observed in SAM and X-ray images. Results of these studies point to changes in the TIM1 modulus during cure and post cure thermal excursions as the cause of the “dark ring” observed in the transmission SAM images rather than delamination at the TIM1/lid or TIM1/die interfaces. However, in the event that delamination is present at the edges it cannot be unambiguously deconvoluted from the “dark ring” artifact in the SAM images.