Little is understood of the anatomical fate of activated T lymphocytes and the consequences they have on the tissues into which they migrate. Previous work has suggested that damaged lymphocytes migrate to the liver. This study compares class I versus class II major histocompatibility complex (MHC)–restricted ovalbumin-specific T cell antigen receptor (TCR) transgenic mice to demonstrate that after in vivo activation with antigen the emergence of CD4−CD8−B220+ T cells occurs more frequently from a CD8+ precursor than from CD4+ T cells. Furthermore, this change in phenotype is conferred only by the high affinity native peptide antigen and not by lower affinity peptide variants. After activation of CD8+ cells with only the high affinity peptide, there is also a dramatically increased number of liver lymphocytes with accompanying extensive hepatocyte damage and elevation of serum aspartate transaminase. This was not observed in mice bearing a class II MHC–restricted TCR. The findings show that CD4−CD8−B220+ T cells preferentially derive from a CD8+ precursor after a high intensity TCR signal. After activation, T cells can migrate to the liver and induce hepatocyte damage, and thereby serve as a model of autoimmune hepatitis.

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IntroductionAs application of microcontrollers to achieve a cost effective system solution becomes more uervasive. demands for higher uerformance and higher functional intemtion continue to incre&e for microcontrollers. s a s h 'EPROM with its electrical reprogr&nability and high density, when integrated on chip, can provide a microcont;oller with enhanced performance and versatility, and offer a more cost effective system solution.This paper presents the development of a 16-bit microcontroller with lOOK bytes of embedded Flash EEPROM, that includes a block erasable flash EEPROM module. Using the SCSG (Source-Coupled Split-Gate) [l] Flash EEPROM cell, the embedded flash memory has achieved a typical program time of 2OpS and erase time of 20mS. The device operates at frequency of over 25MHz.For embedded applications, the criteria for selecting a flash EEPROM cell are different from those for a stand alone flash memory. For stand alone memory, small cell area is often the most critical factor to be considered. For embedded applications, low overall production cost of the microcontroller with integrated flash EEPROM is often the primary concern. For this reason, a robust flaih EEPROM cell that is compatible with the existing host logic process without added tight process controls is a key criterion for use in embedded applications.

Development of new submicron nonvolatile memory modules, including an EEPROM with unique programmable redundancy and a block erasable Flash EEPROM, for 16-bit and 32-bit devices is reported. Optional process modules required for the non-volatile memories are developed for integration into the baseline logic process based on 0 . 6 5 p double metal CMOS technology. INTRODUCTIONIntegration of non-volatile memories has significantly enhanced performance, versatility and applications for microcontrollers. A s technology is further scaled down and the amount of integration capability further increased, larger onchip non-volatile memories are not only required to meet many system applications but also effective for utilizing the added technology capabilities. In this paper, the development of two new submicron nonvolatile memory modules, an EEPROM with unique programmable redundancy and a block erasable Flash EEPROM, for integration into 16-bit and 32-bit devices is reported.