A 512-kb flash EEPROM embedded in a 32-b microcontroller

Kuo, C.; Weidner, M.; Toms, T.; Choe, H.; Chang, Ko-Min; Harwood, A.; Jelemensky, J.; Smith, Philip H.

doi:10.1109/4.126546

Cited by 21 publications

(4 citation statements)

References 8 publications

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“…There are different techniques to manipulate the amount of charge in the FG: using ultraviolet light [10], using tunneling and injection [11,12], and using coupled capacitances [1]. This last option is indicated for the analysis presented here.…”

Section: Multiple-input Floating-gate Metal-oxide-semiconductor Transmentioning

confidence: 99%

“…Subsequently, a new value for V 1 is proposed and a new value of ψ SD,S is obtained and so on until we have a sweep of V 1 . Each obtained value of ψ SD,S in (13) is substituted into (11) to obtain F(ψ SD,S ), and finally a substitution in (10) is performed in order to obtain I DS but now as a function of V 1 .…”

Section: Ds Behavior Of the Multiple-input Floating-gate Metal-oxidmentioning

confidence: 99%

“…List of parameters used in Equations(1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18).…”

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Analysis of the floating‐gate transistor using the charge sheet model

Medina-Vazquez

Meda-Campana

Gurrola-Navarro

et al. 2015

Int J Numerical Modelling

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The multiple-input floating-gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple-input floating-gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple-input floating-gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Figure 2. (a) Intrinsic interface for n-input gates MIFGMOS and (b) MOS interface with a new terminal added (c) capacitances are represented only. 678 A. S. MEDINA-VAZQUEZ ET AL.Figure 3. ψ s vs. (V 1 À V FB ).Simulation results for the intrinsic interface. Voltage V 1 is applied to the control gate CG 1 and swept while V 2 voltage (applied to the control gate CG 2 ) is used as a parameter. V FB = 0.6 V, t ox = 8e À 9 m, W = 0.3 μm, W = 0.1 μm, C 1 = 50 fF, C 2 = 20 fF.

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Section: Multiple-input Floating-gate Metal-oxide-semiconductor Transmentioning

confidence: 99%

Section: Ds Behavior Of the Multiple-input Floating-gate Metal-oxidmentioning

confidence: 99%

See 1 more Smart Citation

Analysis of the floating‐gate transistor using the charge sheet model

Medina-Vazquez

Meda-Campana

Gurrola-Navarro

et al. 2015

Int J Numerical Modelling

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“…The channel-hot-electron injection (CHEI) mechanism has been widely used as a programming technique for nonvolatile memory application in the past [1]. However, owing to the lower programming efficiency, devices utilizing the CHEI mechanism for programming usually need an external high-voltage power supply in order to program the cells within a reasonable time [2][3][4]. Basically, this is due to an inherent incompatibility of having a high hot-carrier generation rate and having an oxide field favourable for electron injection [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

Huang

Fang

Yaung

et al. 1999

Semicond. Sci. Technol.

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In this paper, the mechanism of programming operation considering the source-to-floating gate coupling ratio (SCR) in split-gate source-side injected flash memory has been discussed and experimentally demonstrated. The effects of SCR on the programming performance and cycling endurance have also been investigated in detail. The experimental results indicate that the cell with higher SCR possesses a higher programming speed. Under the same programming speed, the higher-SCR cell shows larger cycling endurance compared to lower-SCR cell.

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Block‐erasing methods for flash memory

Shiba¹,

Kubota²

1994

Electron Comm Jpn Pt II

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Methods for dividing flash memory arrays into erasable blocks of flexible size have been studied. Blocks are partitioned along the word lines and the source lines in different blocks are disconnected. A minimum block is formed along one word lines from which blocks different in volume are constituted easily. In this dividing scheme, the data disturb time of unselected blocks becomes longer, resulting in undesirable threshold reduction. It was found that this data disturb endurance is improved by biasing the source at about 5 V. When the state is “1,” it prevents channel formation so that no hot hole injection into the floating gate takes place. In the case of “0” state, this bias reduces the electric fields between the floating gate and the drain; and hence the F‐N tunneling current is suppressed. By this method, data disturb endurance in unselected blocks was improved to be more than 10, 000 cycles.

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A 512-kb flash EEPROM embedded in a 32-b microcontroller

Cited by 21 publications

References 8 publications

Analysis of the floating‐gate transistor using the charge sheet model

Analysis of the floating‐gate transistor using the charge sheet model

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

Block‐erasing methods for flash memory

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