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This work presents the co-integration of resistive random access memory crossbars within a 180 nm Read-Write CMOS chip.-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of-the-Line. Two different strategies, consisting in insertion of an tunnel barrier layer and the design of a dedicated CMOS read circuit, have been developed in order to increase the cell high-to-low resistance ratio of a factor of 1000 and to reduce the sneak-path current effects by one order of magnitude. The ReRAM cells have been integrated directly on a standard CMOS foundry chip, enabling low cost ReRAM-CMOS integration. The integrated memories show a set and reset voltages of and 1.3 V, respectively. The measured operating voltages are compatible for low-voltage applications.Index Terms-Heterogeneous integration, passive crossbar array, post-processing, read-write circuit, resistive ramdom access memories (ReRAMs).

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The race for performance of integrated circuits is nowadays facing a downscale limitation. To overpass this nanoscale limit, modern transistors with complex geometries have flourished, allowing higher performance and energy efficiency. Accompanying this breakthrough, challenges toward high-performance devices have emerged on each significant step, such as the inhomogeneous coverage issue and thermal-induced short circuit issue of metal silicide formation. In this respect, we developed a two-step organometallic approach for nickel silicide formation under near-ambient temperature. Transmission electron and atomic force microscopy show the formation of a homogeneous and conformal layer of NiSi on pristine silicon surface. Post-treatment decreases the carbon content to a level similar to what is found for the original wafer (∼6%). X-ray photoelectron spectroscopy also reveals an increasing ratio of Si content in the layer after annealing, which is shown to be NiSi according to X-ray absorption spectroscopy investigation on a Si nanoparticle model. I-V characteristic fitting reveals that this NiSi layer exhibits a competitive Schottky barrier height of 0.41 eV and series resistance of 8.5 Ω, thus opening an alternative low-temperature route for metal silicide formation on advanced devices.