Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

Abstract

This work presents the co-integration of resistive random access memory crossbars within a 180 nm Read-Write CMOS chip.-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of-the-Line. Two different strategies, consisting in insertion of an tunnel barrier layer and the design of a dedicated CMOS read circuit, have been developed in order to increase the cell high-to-low resistance ratio of a factor of 1000 and to reduce the sneak-path current effects by one order of magnitude. The ReRAM cells have been integrated directly on a standard CMOS foundry chip, enabling low cost ReRAM-CMOS integration. The integrated memories show a set and reset voltages of and 1.3 V, respectively. The measured operating voltages are compatible for low-voltage applications.Index Terms-Heterogeneous integration, passive crossbar array, post-processing, read-write circuit, resistive ramdom access memories (ReRAMs).

A neuromorphic systems approach to in-memory computing with non-ideal memristive devices: from mitigation to exploitation

“…For example, it is not clear how much passive cross-bar arrays can be scaled up to larger sizes, due to sneak path and cross-talk issues 17 . Even in the case of crossbar arrays with active elements such as 1T-1R (one-transistor and one-memristor) or memristive devices with embedded "selectors" used to avoid the sneak-path problem, issues such as the line resistance, reproducibility, and overhead size of external encoder and decoder CMOS circuits 19 are yet to be satisfactorily addressed. Alternatively, one can decide to forgo the cross-bar approach of very high density arrangements of basic 1R or 1T-1R elements, and design addressable arrays of more complex synapses that comprise multiple transistors and multiple memristive devices per synapse, to try and capitalize on the many other useful features of memristive devices (in addition to their compact size), such as non-volatility, state-dependence, complex physics that can be exploited to emulate the complex molecular properties of biological synapses, complex dynamics, and stochastic behavior.…”

“…In many of these systems, and in particular in neuromorphic processing devices designed to overcome the von-Neumann bottleneck problem 7,8,[10][11][12][13][14] , the bulk of the silicon real-estate is taken up by synaptic circuits that integrate in the same area both memory and computational primitives. To save area and maximize density in such devices, one possible approach is to implement very basic synapse circuits arranged in dense cross-bar arrays [15][16][17][18][19] . However, such approach is likely to relegate the role of the synapse to a a Address, Address, Town, Country.…”

In-Memory Data Parallel Processor

“…For this operation we reverse the voltage across memristor bit-cell. Fortunately, several reports on fabricated ReRAM demonstrate the symmetric V/I properties of memristor with reverse voltage across terminals [36,44].…”

Architectures and automation for beyond-CMOS technologies

“…Figure 2.4a shows a 0T1R or simple a 1R configuration. This configuration has been realized by multiple physical prototypes [31,39,40]. However, the size of the crossbars are severely limited due to presence of parasitic current [41].…”