A new low-temperature polysilicon high-voltage LDMOS (LTPS HVLDMOS) using excimer laser crystallization has been proposed for the first time. However, in order to enhance LTPS HVLDMOS characteristics, there are two starting points: 1) integrate the thin-film technology with the power device, and 2) clarify the requirement of excimer laser treatment for low-temperature power devices. As the result, the on/off current ratio after laser treatment is improved over 10 6 times than that before laser treatment at drift = 15 m and ds = 25 V. The LTPS HVLDMOS after laser treatment also demonstrates the better tradeoff between the specific on resistance and breakdown voltage against the previous high-voltage thin-film transistors (HVTFTs) by solid-phase crystallization-such as semi-insulating (SI), metal field-plated, and offset-drain HVTFTs. Index Terms-Excimer laser crystallization (ELC), high-voltage thin-film transistor (HVTFT), lateral double diffused MOS (LDMOS), low-temperature polycrystalline silicon (LTPS).

The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (BV) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the BV and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

Many high voltage complementary metal-oxide-semiconductor (HV-CMOS) processes are modified from a standard 5 V CMOS process by adding an N-type heavily doped layer under the P-well of a HV-PMOS drain terminal to isolate a high voltage P-well from a grounded P-substrate. The limitation of breakdown voltage is dominated by P-well concentration and junction depth. For designing a certain breakdown voltage (BV dss ) for a HV-PMOS, the original 5 V CMOS P-well concentration should be decreased, which could degrade 5 V CMOS characteristics, such as NMOS punch through and latchup immunity. In this study, we demonstrate a novel HV-PMOS based on a split N-type buried layer (NBL), which provides a high BV dss in a HV-CMOS process. The newly proposed device with NBL split under the P-well of a drain electrode increases BV dss without degrading specific on-resistance (R on,sp ) and any added process complexity. From this result, P-well concentration could be increased to improve both 5 V NMOS characteristics and HV-PMOS R on,sp .

In this study, a novel termination is designed in a low-voltage N-channel trench power metal-oxide-semiconductor fieldeffect transistor (MOSFET) to simplify the fabricating process. In a conventional trench power-MOSFET (PowerMOS), a field oxide with a metal field plate is often used for edge termination. The field oxide only exists in the termination region of the trench PowerMOS; therefore if the termination can be designed without the field oxide, field oxidation can be removed from the fabrication. Trench termination is proposed in this work to replace field oxide termination. The use of multiple trench rings leads to the desired breakdown voltage. The temperature effect in trench termination must be considered owing to the negative coefficient of the threshold voltage (V TH ) of the P-type MOS (PMOS) and the temperature. This work also provides a design guideline for trench termination in the low-voltage trench PowerMOS.

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