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The effects of different polishing pads and slurry solid contents on the SiGe chemical mechanical polish ͑CMP͒ process were investigated. By optimizing the polishing conditions, a smooth strained-Si surface on a flattened Si 0.8 Ge 0.2 buffer layer of 0.6 nm can be achieved. The novel cleaning solutions with various surfactants and chelating agents for post-CMP SiGe were studied. There was about 10% current enhancement of the optimal cleaning conditions, showing high performance in particle removal, metallic cleaning, and electrical characteristics.Strained silicon on relaxed silicon-germanium ͑SiGe͒ substrates is a promising candidate for transistor performance enhancement. 1 Strain splits the degeneracy in the conduction and valence bands of Si, enhances the transport properties of electrons and holes, and provides transistor speed enhancement. High-quality strainedrelaxed buffer layers are required for high-performance devices, but the relaxed SiGe layers tend to have threading dislocations and rough surfaces. Several methods such as the graded buffer layers 2,3 and low-temperature buffer 4 methods have been studied. Relaxation during the growth of the visual substrate results in a crosshatch ͑misfit dislocations͒ which increases surface roughness. The chemical mechanical polishing ͑CMP͒ process has become the mainstream of global planarization techniques in fabrication of deep submicrometer integrated circuits. To reduce surface roughness, the CMP process is being applied to the grown layers. A few researchers have introduced it into polishing SiGe buffer layers. 5-9 The high crystalline quality of the regrowth layer with a smooth interface makes it possible to fabricate high-performance SiGe devices with low surface roughness scattering. However, the wafer surface after the CMP process is seriously contaminated with particles and metallic impurities from the polishing slurry. In addition, the metallic impurities induce many crystal defects in the Si wafers during thermal processing, 10 and planarized SiGe buffer layer roughness is increased due to the etching effect. 11 Our previous studies have found that the novel post-CMP cleaning solution can significantly reduce contamination retention. 12,13 The surfactant tetramethylammonium hydroxide ͑TMAH͒ and the chelating agent ethylenediaminetetraacetic acid ͑EDTA͒ were used to enhance the removal efficiency of particle and metal impurities. We found that removal efficiency of particle and metallic impurities was enhanced by post-poly-Si CMP cleaning. The electrical characteristics can be also improved by the novel post-CMP solution. In this paper, we applied the post-CMP cleaning on SiGe buffer layers. Furthermore, the capacitor and metal oxide semiconductor field effect transistor ͑MOSFET͒ electrical characteristics of strained-Si regrowth on the substrate treated with various solutions were also evaluated. ExperimentalThe SiGe epitaxy layers on 6-in.-diam Si͑100͒ substrates were prepared by ultrahigh-vacuum chemical vapor deposition ͑UHV-CVD͒. The novel relaxe...

We demonstrate the fabrication process and the electrical characteristics of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) with different numbers of channel stripes. The device's electrical characteristics, such as on-current, threshold voltage, and subthreshold swing, were improved by increasing the number of channel stripes due to the enhancement of gate control. However, the electric field strength near the drain side was enlarged in multi-channel structures, causing severe impact ionization. The degradation of device's reliability under various electrical stress conditions was suggested.

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