-In this contribution a C-Band 2 nd harmonic tuned hybrid power amplifier utilizing a PHEMT GaN device is presented, together with technological aspects, non linear device model and adopted design criteria. The amplifier has been realised in hybrid form, exhibiting a bandwidth larger than 20% around 5.5GHz, with a minimum output power of 33 dBm, and a drain efficiency of 60% at the centre frequency.

Abstract—A major limitation in the performances of\ud AlGaN/GaN high-electron mobility transistors (HEMTs) is\ud due to self heating effects, connected to the efficiency of heat\ud removal from the device. In this paper, we present a new experimental\ud investigation on the thermal handling capabilities of\ud AlGaN/GaN HEMTs, with conventional and flip-chip bonding.\ud Efficient photocurrent measurements were performed in order to\ud extract directly the channel temperature for all the device configurations.\ud We were able to measure devices realized on sapphire\ud substrate both with conventional and flip-chip bonding, and to\ud compare them with devices on SiC substrate with conventional\ud bonding, demonstrating that flip-chip bonding allows to achieve\ud almost the same results that SiC substrate. Measured results are\ud in good agreement with the presented simulation data

-In this contribution a C-Band 2 nd harmonic tuned hybrid power amplifier utilizing a PHEMT GaN device is presented, together with technological aspects, non linear device model and adopted design criteria. The amplifier has been realised in hybrid form, exhibiting a bandwidth larger than 20% around 5.5GHz, with a minimum output power of 33 dBm, and a drain efficiency of 60% at the centre frequency.

A complete design flow starting from the technological process development up to the fabrication of digital circuits is presented. The aim of this work is to demonstrate the GaAs Enhancement/Depletion (E/D) double stop-etch technology implementation feasibility for digital applications, aimed at mixed signal circuit integration. On the basis of the characterization of small E/D devices with different Gate peripheries, developed by the SELEX-SI foundry, and the analysis of several GaAs-based logical families, the most suitable logic for the available technology has been selected. Then, simple test vehicles (level shifters, NOR logic gates and D Flip-Flops) have been designed, realized, and measured to validate the design strategy applied to the GaAs E/D process. These logical circuits are preliminary to the design of a more complex serial-to-parallel converter, to be implemented onto the same chip together with RF analog blocks, such as stepped attenuators and phase shifters.

The design, fabrication and test of X-band high-power monolithic SPDT switches in microstrip GaN technology Lire presented. Such switches have demonstrated state-of-the-art performance: they exhibit I dB on-state insertion loss and better than 37 dB isolation. power-handling measurements have shown that no compression phenomenon occurs with an input power equal to 39.5 dBm at 10 GHz