Via bottom void is one of the problems related to the metal interconnections in semiconductor devices. In 0.13μm technology, Novellus Sabre serial is wildly applied as copper(Cu) electro chemical plating (ECP) tool, but the problem of high hit ratio of via bottom void in 90nm CMOS technology makes it difficult to perform as well as in the 0.13μm technology. In this paper, the mechanism of the formation of via bottom void of Cu interconnection was analyzed and the solution of the problem in the 90nm technology was studied. A series of experiments were carried out and the result shown that the via bottom void can be eliminated by increasing the plating current during the initial period of Cu plating process.

Hillock is formed at the film surface in Cu metallization process. During the growth of hillock, the tensile stress built in the copper (Cu) metal film due to the relieved thermal expansion coefficients. These "hillocks" are just areas of localized copper elevation relative to the rest of the surface that can lead to non-uniformity during etch-stop dielectric deposition. It is important to understand how the hillock is created in order to develop an effective preventative process. In this paper, the degas temperature performance and effect on the hillock in Cu metallization process is introduced, then an effective approach to reduce hillock defect is demonstrated.

Copper (Cu) material is being widely used in the advance ultra large-scale integration (ULSI) in the metallization process due to its low resistivity and good performance on EM in 130nm and below technology node. In Cu metallization process of 130nm, crescent pits defect on wafer edge is often scanned and found post Cu CMP process. Thus interconnect reliability and yield loss become key issue to ensure device quality and performance. In the filed, some studies focus on the Cu plating wetting ability improvement to reduce pits defect. In this paper, atmosphere VOC (Vapor Organic Compound) effect is studied to reduce crescent pits formation.

TSV (Through Silicon Via) is a new method for 3D technology (IC integration). Different chips can be connected with the Cu line through silicon substrate. Via area is so deep (usually 100-300um) that we need thicker barrier and seed layer. The Cu plating is the key step in TSV flow. But we suffered TSV void issue in TSV ECD (Electro Chemical Deposition ) process for TSV seed layer poor condition impact .It is important to understand how to improve TSV Cu plating gap fill capability in order to develop TSV technology. In this paper, the barrier and seed layer performance improvement in TSV Cu plating is introduced, and then an effective approach to improve the TSV plating gap fill capability is demonstrated.

In copper metallization of BEOL, ECP is used for copper deposition in via or trench for interconnection after PVD barrier & seed process. But ECP film easily suffers pits defect with swirl pattern that is a killer defect to CP yield. This paper introduces a method to greatly reduce swirl defect by improving the wetting ability between Cu seed film and ECP chemicals.