The decision by the Semiconductor Industry Association (SIA) to accelerate the continuing evolution to smaller linewidths is consistent with the commitment by Etec Systems, Inc. to rapidly develop new technologies for pattern generation systems with improved resolution, critical dimension (CD) uniformity, positional accuracy, and throughput. Current pattern generation designs are inadequate to meet the more advanced requirements for masks, particularly at or below the 100 nm node. Major changes to all pattern generation tools will be essential to meet future market requirements.An electron-beam (e-beam) system that is designed to meet the challenges for 1 30-100 nm device generation with extendibility to the 70-nm range will be discussed. This system has an architecture that includes a graybeam writing strategy, a new stage system, and improved thermal management. Detailed changes include a pulse width modulated blanking system, per-pixel deflection, retrograde scanning, multipass writing, and a column with a 50 kV accelerating voltage that supports a dose of up to 45 MC/cm2 with minimal amounts of resist heating. This paper examines current issues, our approach to meeting International Technology Roadmap for Semiconductors (ITRS) requirements, and some preliminary results from a new pattern generator.
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