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For the fust time, 512Mb DRAMS using a RecessCnannel-AnayTrrmsi~to@XAT) are successfully developed with 88nm feature size, which is the smalllest feature size ever reported DRAM technology with non-planar amy huistor. The RCAT with gate length of 75nm and recessed charmel depth of 1 5 h exhibits mastlcally improved electrical charactenstics such as DIBL, BV, junction leakage and cell conmcl resistance, comparing to a wnventional planar a m y bansistor of the sarne gate length. 'he mst powetful effect using the K A T m DRAMS is a great impmvemnt of data retention time. In addition, this technology will easily extend to suh7Gnm node by simply inneasing reoessed charmel depth and kecpmg the same dopmg mcenhation of the subsbate. lntmductionAs DRAM tedmology enters into suhlM)nm node and reaches to sub7Onm node, it becomes m o~e and more serious challenge to obtajn sufficient data retention time It is basically due to the increased subdoping wnmbabn wnh s h h g of feature si ze, whch result.; in increased eleceic field and junction leakage c m m t as shown Fig.1. The simplest way to reduce s u b a t e doping is probably to increase channel length Gff) of cell & " I . Fmm that point of view, deal access b a n s i s t m which are slitable for h c h capacitor stlucblre, have been pmposed.[l] However it is generally believed that the vertlcal m y " i s t o r is mne wmplicatd to fabricate than planar cell myh-rmsistor, and t h d y increased process cost. Aiming to increase Leff while &mining planar cell m y bansistor, for the lirst tim, we develop the RCAT m u m in stack capacitor cells and demonsbate the qxrionty of RCAT. The wnap of the RCAT is to inrredse Leff hy-g channel from d i w n d a c e . As a mlt, it wn greatly d u c e channel doping density, thereby reducing s/D resistmce of m~l a r y cell and enhancing Cirmer mobilay, whim czn ampemate deaeased cauxd by longer Leff of RCAT. Lower s u h t e dopmg c o n m~o n and d l e r eleceic field on "ge node junction when RCAT is used are clearly shown in Fig1 and F i e respectively In this p~per, key process technologies of the RCAT are developed with 8 8 m feature size which is the Smallest dunenslon of DRAM e m m e d . And Oumrmdmg charaftenstics of RCAT are v t d .Key pmces techndogies of the RCAT. The procesr mtegndion for the R C X is well illushateed in Fig. 3. And nosssedional SEM of l l l y mtegmted cell is shown in Fig.4. Although the recess channel msistor is applied to cell amy re&ons, the conventional planar trrmSstm ae Sill used for s t q a t i regions. For the formation of mess channel, ihn oxide layer and thick poly layer are depmtcd on the subshate as a mask l a p . Several key technolo@es of the KCATare surmranzedbelow.A. Poaeming UJIPC~SS chnnnd using ArF IitJzopnphy for 75nm rdarmymns&ior.ArF lithogaphy is used for defmmg 55-nm space pattemi,Lnpen) to be Tecessed channel w o n for 75mn cell a m y bwsistor as shown in Fig5 'lhere are two stlu&m to form Tecessed channel. One is, we call is Inner-gate sbucture where gate dimension(Lgate) is smaller than Lo...

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Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si,NI, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs.