S. Iwata scite author profile

The GMICRO/~OO, a 32-bit microprocessor based on the TRON architecture specification, has high performance bit-map manipulation instructions. The bit-map instructions are implemented by pipelining micro-operations and achieve optimum use of the memory bus in the execution. The bit-map instructions are 2 t o 3 times faster than repeating move instruction by the software. Microprogram development tools for the G M I C R O /~~~ design are also described in this paper.

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S. Iwata

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The approach to multiple instruction execution in the GMICRO/400 processor

A 32-bit microprocessor with high performance bit-map manipulation instructions

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