A 300 kbit bubble memory chip has been designed based on 3 μm bubble technology. Nominal circuit period is 14 μm and chip size is 9.8 mm×9.6 mm. A gap-tolerant design is fully employed, such as, asymmetric half-disk propagation pattern, half-disk transfer gate, a novel asymmetric-chevron stretcher, etc. The chip is fabricated using a new planar process solving step-coverage problems to achieve good process yield. A typical bias field margin of 18 Oe is obtained at 55 Oe with a triangular wave drive.

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A 3 µm bubble 80 kbit chip was designed by 1/2 scaling from the pattern for 6 µm bubble chip. To obtain a 1 µm minimum feature over a 5 mm square, projection printing was employed. By reducing the reflectance of the surface to be exposed below 33%, standing wave effects with monochromatic illumination could be minimized, and uniform 2 µm width and 1 µm gap pattern could be obtained, notwithstanding the variation in photoresist thickness and the unevenness of substrate. A standard deviation of this distribution in the pattern gap width in the fabricated 80 kbit chips was 0.067 µm when the flatness of the wafer is less than 0.5 µm/chip size. The effects of the variation in the pattern gap on the propagate margins could be ignored, if it fell in the range of 1.03 µm to 1.38 µm. Consequently, the resolution of 1±0.3 µm and uniform bias margin over 80 kbit chip area could be achieved with high yield.

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A newly developed heat resistant resin, ladder type organosiloxane polymer, is applied to 8 μm period 1 megabit bubble memory devices. Propagation bias margin and reliability are discussed, comparing with the conventional SiO lift-off planar process. TaMo alloy-Au system is also introduced for the conductor. Interdiffusion, electromigration, and corrosion resistance of Au and refractory metals are studied.