Successful integration of 100V LDMOS devices in 0.35µm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide.

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For the first time, this paper analyzes the turn-off behavior of the planar 1.2 kV/25, a nonpunch-through clustered insulated gate bipolar transistor (NPT-CIGBT) under clamped inductive load switching, in detail and through experiment simulation. Turn-off behavior of the CIGBT involves strong interaction between device and circuit parameters. The circuit parameter such as gate resistance was varied in order to observe the dI/dt, dV/dt, and turn-off energy loss of the device. Experimental results are shown at 25 C and 125 C. In addition, numerical simulation results are used to enhance understanding of the internal physics of the NPT-CIGBT turn-off process.

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