Fault tolerance has long been a major concern for sensor communications in fault-tolerant cyber physical systems (CPSs). Network failure problems often occur in wireless sensor networks (WSNs) due to various factors such as the insufficient power of sensor nodes, the dislocation of sensor nodes, the unstable state of wireless links, and unpredictable environmental interference. Fault tolerance is thus one of the key requirements for data communications in WSN applications. This paper proposes a novel path redundancy-based algorithm, called dual separate paths (DSP), that provides fault-tolerant communication with the improvement of the network traffic performance for WSN applications, such as fault-tolerant CPSs. The proposed DSP algorithm establishes two separate paths between a source and a destination in a network based on the network topology information. These paths are node-disjoint paths and have optimal path distances. Unicast frames are delivered from the source to the destination in the network through the dual paths, providing fault-tolerant communication and reducing redundant unicast traffic for the network. The DSP algorithm can be applied to wired and wireless networks, such as WSNs, to provide seamless fault-tolerant communication for mission-critical and life-critical applications such as fault-tolerant CPSs. The analyzed and simulated results show that the DSP-based approach not only provides fault-tolerant communication, but also improves network traffic performance. For the case study in this paper, when the DSP algorithm was applied to high-availability seamless redundancy (HSR) networks, the proposed DSP-based approach reduced the network traffic by 80% to 88% compared with the standard HSR protocol, thus improving network traffic performance.

Abstract:In this paper, we propose a very effectively filtering approach (EFA) to enhance network traffic performance for high-availability seamless redundancy (HSR) protocol in smart grids. The EFA combines a novel filtering technique for QuadBox rings (FQR) with two existing filtering techniques, including quick removing (QR) and port locking (PL), to effectively reduce redundant unicast traffic within HSR networks. The EFA filters unicast traffic for both unused terminal rings by using the PL technique and unused QuadBox rings based on the newly-proposed FQR technique. In addition, by using the QR technique, the EFA prevents the unicast frames from being duplicated and circulated in rings; the EFA thus significantly reduces redundant unicast traffic in HSR networks compared with the standard HSR protocol and existing traffic filtering techniques. The EFA also reduces control overhead compared with the filtering HSR traffic (FHT) technique. In this study, the performance of EFA was analyzed, evaluated, and compared to that of the standard HSR protocol and existing techniques, and various simulations were conducted to validate the performance analysis. The analytical and simulation results showed that for the sample networks, the proposed EFA reduced network unicast traffic by 80% compared with the standard HSR protocol and by 26-62% compared with existing techniques. The proposed EFA also reduced control overhead by up to 90% compared with the FHT, thus decreasing control overhead, freeing up network bandwidth, and improving network traffic performance.

Mobile ad hoc networks (MANETs) are particularly suited for scenarios that demand rapid deployment of a communication system without any existing network resources. For instance, a MANET can facilitate the intercommunication process between members of a rescue party in a natural disaster, where the underlying routing protocol is crucial to maintaining the dissemination capability of data-critical packets. However, the backbone of every MANET, i.e., their routing protocol, is limited by the communication range of nodes, their high-speed mobility, and the capacity constraints of energy. This study proposed a fault-tolerant ad hoc on-demand routing protocol (FT-AORP) that relies on these characteristics of MANET nodes to determine reliable paths for data transmission. Subsequently, two of the discovered paths were used to transmit the duplicates of an original data packet to maximize fault tolerance. Further, using the OMNeT++ network simulator, the performance of the proposed system was evaluated through extensive simulation experiments against three simulation parameters: the number of network nodes, node speed, and data packet sending rate. The simulation results demonstrated that FT-AORP greatly improved the packet delivery ratio, reduced end-to-end delay, and maintained a higher residual energy level of the transmission path, compared to other baseline routing protocols.INDEX TERMS Mobile ad hoc network, fault tolerance, network mobility, on-demand routing protocol.

A conventional coordinate rotation digital computer (CORDIC) has a low throughput rate due to its recursive implementation of micro-rotations. On the contrary, a fully-pipelined cascaded CORDIC provides a very high throughput rate at the cost of high complexity and large area. In this paper, possible design choices of cascaded CORDIC are explored over a wide range of operating frequencies, throughput rates, latency, and area complexity. For this purpose, we present a fine-grained critical path analysis of the cascaded CORDIC in terms of bit-level delay. Based on the propagation delay estimate, we propose an algorithm for determining the required number of pipeline stages and locations of the pipeline registers in order to meet the time constraint in a particular application. A hybrid cascaded-recursive CORDIC is also proposed to increase the throughput rate, and to reduce the latency and energy per sample (EPS). From synthesis results, we show that the proposed pipelined cascaded CORDIC with only four pipeline stages requires 31.1% less area and 29.0% less EPS compared to a fully-pipelined CORDIC. An eight stage pipelined recursive cascaded CORDIC provides 18.3% less EPS and 40.4% less area-delay product than a conventional CORDIC.

In this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be configured for the computation of the DCT of any of the prescribed lengths such as 4, 8, 16, and 32. It is shown that matrix multiplication schemes involving fewer adders can be used to derive parallel architectures for 1D integer DCT of different lengths. A novel transposition buffer is designed to be used for the proposed 2D DCT architecture, which offers double the throughput without increasing the size of the transposition buffer. We determine the optimal pipeline locations in the proposed design through the precise estimation of propagation delays and the critical path so that the area-delay-product is optimized and all the output samples are obtained in the same cycle in spite of the recursive nature of the structure. Implementation results show that the proposed 2D integer DCT architectures provide significantly higher throughput per unit area than the existing designs for HEVC.