In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

No abstract

We describe methods to determine transfer functions for line edge roughness (LER) from the photoresist pattern through the etch process into the underlying substrate. Both image fading techniques and more conventional focus-exposure matrix methods may be employed to determine the dependence of photoresist LER on the image-log-slope (ILS) or resist-edge-log-slope (RELS) of the aerial image. Post-etch LER measurements in polysilicon are similarly correlated to the ILS used to pattern the resist. From these two relationships, a transfer function may be derived to quantify the magnitude of LER that transfers into the polysilicon underlayer from the photoresist. 1 A second transfer function may be derived from power spectral density (PSD) analysis of LER. This approach is desirable based on observations of pronounced etch smoothing of roughness in specific spatial frequency ranges.Smoothing functions and signal averaging of large numbers of line edges are required to partially compensate for large uncertainties in fast-Fourier transform derived PSDs of single line edges. An alternative and promising approach is to derive transfer functions from PSDs estimated using autoregressive algorithms.The utility of these methods to several photoresist and etch processes will be described.

In this study, we discuss modeling finite laser bandwidth for application to optical proximity modeling and correction. We discuss the accuracy of commonly-used approximations to the laser spectrum shape, namely the modified Lorentzian and Gaussian forms compared to using measurement-derived laser fingerprints. In this work, we show that the use of the common analytic functions can induce edge placement errors of several nanometers compared to the measured data and therefore do not offer significant improvement compared to the monochromatic assumption. On the other hand, the highlyaccurate laser spectrum data can be reduced to a manageable number of samples and still result in sub 0.5nm error through pitch and focus compared to measured spectra. We have previously demonstrated that a 23-point approximation to the laser data can be generated from the spectrometry data, which results in less than 0.1nm RMS error even over varied illumination settings. We investigate the further reduction in number of spectral samples down to five points and consider the resulting accuracy and model-robustness tradeoffs. We also extend our analysis as a function of numerical aperture and illumination setting to quantify the model robustness of the physical approximations. Given that adding information about the laser spectrum would primarily impact the model-generation run-times and not the run-times for the OPC implementation, these techniques should be straightforward to integrate with current full-chip OPC flows. Finally, we compare the relative performance of a monochromatic model, a 5-point laser-spectral fingerprint, and two Modified Lorentzian fits in a commercial OPC simulator for a 32nm logic lithography process. The model performance is compared at nominal process settings as well as through dose, focus and mask bias. Our conclusions point to the direction for integration of this approach within the framework of existing EDA tools and flows for OPC model generation and process-variability verification.

No abstract