No abstract

A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MOS transistors within each pixel to buffer the photo-signal, enhance sensitivity, and suppress noise. The pixel size is 20 im X 20 jm and was implemented in a standard digital 0.9 pm single-polysilicon, double-metal, n-well CMOS process; leading to 25% fill-factor. Row and column decoders and counters are monolithically integrated as well as per column analog signal correlated double-sampling (CDS) processors, yielding a total chip size of approximately 4.5 mm X 5.0 mm. The image sensor features random accessibility and can be employed for electronic panning applications. It is powered from a single 5.0 V source.At 5.0 V power supply, the video signal saturation level is approximately 1,200 mV with rms read-out noise level of approximately 300 jiM, yielding a dynamic range of 72 dB (12 bits).The read-out sensitivity is approximately 6.75 jiV per electron, indicating a read-out node capacitance of approximately 24 fF which is consistent with the extracted value. The measured dark current (at room temperature) is approximately 160 mVIs, equivalent to 3.3 nA/cm2. The raw fixed pattern noise (exhibited as column-wise streaks) is approximately 20 mV (peak-to-peak) or approximately 1.67% of saturation level. At 15 frames per second, the power dissipation is approximately 75 mW. 0-8194-1 762-9195/$6.00 SPIE Vol. 2415 / 265 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/26/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

No abstract

The design of a CCD image half-toner integrated monolithically on the focal plane with a 256 X 256 frame transfer imager is reported and the algorithm used is discussed. The imager/half-toner chip is projected to achieve a throughput of 30 frames per second.

A focal-plane-array chip designed for real-time, general-purpose, image preprocessing is reported. A 48 X 48 pixel detector array and a 24 X 24 processing element processor array are monolithically integrated on the chip. The analog, charge-coupled device-based VLSI chip operates in the charge domain and has sensing, storing, and computing capabilities. The chip was fabricated with a double-poly, double-metal process in a commercial CCD foundry. The simulation of an edge detection algorithm implemented by the chip is presented. An overview of the chip performance is described as well.