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Modern high-speed wireless data links such as 60GHz RF and point-to-point communications activate research on Gb/s transceivers for V-band (50 to 75GHz) and W-band (75 to 110GHz). Conventional approaches in SiGe or III-V compounds simply consume too much power and occupy too large area, in addition to the integration difficulty. In CMOS realizations, baseband processors and high-speed digitizers also increase design complexity and power consumption. This paper introduces a fully integrated CMOS QPSK transceiver with baseband-less carrier-and data-recovery circuitry, significantly reducing power consumption while achieving up to 3.5Gb/s data rate.The QPSK transmitter is shown in Fig. 9.5.1. Providing a prototype for the 81-to-86GHz band and 94GHz band, we set up the carrier at 87GHz. An integer-N frequency synthesizer provides 77.3GHz LO and 9.7GHz IF signals, forming an 8/9-1/9 up-convert architecture. It contains a VCO running at 77.3GHz, ÷8 and ÷16 circuits, a type-IV PFD, a V-to-I converter, and an on-chip 2nd-order loop filter. The frequency arrangement is also applied to the RX, making no potential frequency offset between the two. A QPSK modulator generates 4 phases (0°, 90°, 180°, and 270°) of the 9.7GHz IF signal and sends them to the up-convert mixer, creating the 87GHz RF signal. A mm-Wave balun converts differential RF inputs into single-ended mode to drive the PA. With the input capacitance of M 1 and M 2 absorbed by the mixer's resonance network, the balun achieves conversion loss of 1.4dB if the transformer coupling factor is 0.6. The PA's output is fed into a matched microstrip line, which connects to the waveguide adapter.To perform coherent demodulation, the LO clock in the RX must be synchronized in phase and frequency. Unlike typical baseband approaches that require highspeed ADCs (several GS/s) and signal processors (>1GHz), we realize the carrier recovery in the analog domain (i.e., Costas loop). As depicted in Fig. 9.5.2, the receiver is composed of an LNA, a down-convert mixer, an IF amplifier, a 77.3GHz clock source (VCO) and its ÷8 descendants (9.7GHz I/Q signals), and a phase detector (PD) and a frequency detector (FD) for carrier recovery. After LNA amplification, the incoming RF signal is downconverted into IF by the VCO's clock. Assuming the signal at node A is given bywhere D I , D Q denote the embedded data, ω IF is the LO 2 frequency (=2π×9.7GHz), and Δφ is the phase error between IF and LO 2 . After mixing and limiting, the two outputs V D (t) and V E (t) become D I (t) and D Q (t), respectively, given that −45°<Δφ<45°. The V C (V B ) and V D (V E ) are further mixed together, creating the final output V F proportional to sin(Δφ). As a result, the (V/I) 1 's output I CP1 presents a sinusoidal characteristic as shown in the upper-left corner of Fig. 9.5.2. Denoting pumping current as I P when Δφ = π/4, the PD [together with (V/I) 1 ] gain is given by √2I P . The approximately linear behavior in the vicinity of the origin makes itself a linear PLL with two correlated phase-adjusting...