Silicon carbide (SiC) has a range of useful physical, mechanical and electronic properties that make it a promising material for next-generation electronic devices. Careful consideration of the thermal conditions in which SiC [0001] is grown has resulted in improvements in crystal diameter and quality: the quantity of macroscopic defects such as hollow core dislocations (micropipes), inclusions, small-angle boundaries and long-range lattice warp has been reduced. But some macroscopic defects (about 1-10 cm(-2)) and a large density of elementary dislocations (approximately 10(4) cm(-2)), such as edge, basal plane and screw dislocations, remain within the crystal, and have so far prevented the realization of high-efficiency, reliable electronic devices in SiC (refs 12-16). Here we report a method, inspired by the dislocation structure of SiC grown perpendicular to the c-axis (a-face growth), to reduce the number of dislocations in SiC single crystals by two to three orders of magnitude, rendering them virtually dislocation-free. These substrates will promote the development of high-power SiC devices and reduce energy losses of the resulting electrical systems.

We succeeded in measuring the density and direction of the edge component of threading dislocations (TDs) in c-plane (0001) GaN by micro-Raman spectroscopy mapping. In the micro-Raman spectroscopy mapping of the E2H peak shift between 567.85 and 567.75 cm−1, six different contrast images are observed toward directions of . By comparing X-ray topography and etch pit images, the E2H peak shift is observed where the edge component of TDs exists. In contrast, the E2H peak is not observed where the screw component of TDs exists.

A new design and processing concepts have been applied to develop practical SiC trench MOSFETs for high power applications. The designed trench MOSFET has a MOS structure consisting of epitaxially grown n‐type SiC trench sidewall layers. The current flows via an accumulation mode through the channel defined in the epitaxially grown SiC sidewall layer. The channel is depleted by the built‐in fields of the p‐type SiC base layer and the p‐poly‐Si gate, that control the channel conditions. The simulation based investigations revealed that the formed channel can withstand up to the avalanche breakdown condition. The structure of the n‐type SiC trench sidewall epi‐layer has been optimized to realize the blocking voltage of more than 1000 V for SiC MOSFETs with low on‐state resistance. Moreover, our designed structure can address most of the open issues related to the MOS interface, viz., high surface state density, low channel mobility and high electric field at the trench base of the MOS structure. We have fabricated the first 2 mm square large size 6H‐SiC trench MOSFET chip, in which 2380 hexagonal structural microcells of 23 μm pitch were integrated. The fabricated 6H‐SiC trench MOSFET on (0001‐) C‐face wafers feature the on‐state resistance as low as 23.84 m Ω cm2 with blocking voltage of more than 450 V.

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