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The present tendency toward devices scaling i n VLSI technology makes more and more dificult the electrical characterization of channel dimenrions. The narrow channel effects have had a great consideration for what concern device modeling, but a minor attention about dimensional loss problems. The aim of this work is to propoJe an effective width characterization method based on transconductance and not affected by the typical problems related to narrow channel devices. Moreover, a compared analysis of this method to an other one previously proposed [ I ] i3 shown pointing out the phenomenological differences.

The influence of different layout parameters on latchup susceptibility was studied on standard four-stripes test structures fabricated using two bulk processes: standard n-well and a twin-tub technology. Twin-tub structures show increased latchup hardness and guard-ring effectiveness, mainly due to the increased doping level and the consequent decrease in substrate and well resistances. Standard and twin-tub structures show marked three-dimensional effects in the holding characteristics, which lead to an uneven distribution of the latchup current within test structures and hysteresis in the I-V characteristics

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The SWAMI (side wall masked isolation) technique has been implemented in several VLSI and ULSI process outlines, as it is characterized by a low bird's beak extension, interesting topographical features such as a smooth top surface after field oxidation, and a low substrate defect density. In this work both the structural properties and electrical characteristics of single and double silicon etched SWAMI techniques are investigated. A comparison is also made with standard LOCOS isolation techniques. It will be demonstrated that the double silicon etch SWAMI structure is a very appropriate isolation alternative for standard LOCOS. The good electrical performance coupled with the geometry advantages, i.e., a high planarization level and a low bird's beak extension, make SWAMI a suitable isolation technique for future ULSI processing schemes.