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In patterning the via-hole, uneven hole-size and missing-hole defects were identified through after etch inspection (AEI), and these defects were characterized as yield killer since it led to electrical open. Through the after development inspection (ADI) and AEI comparison, the uneven hole-size and missing-hole defects are attributed to the postdeveloped satellite spots. The distribution of satellite spots always show a strong photo field map that is discovered to correlate with the local pattern density in mask scribe lane. Apart from the possible modifications on pattern density in the scribe lane by retooling the photo mask, this paper describes the work done in reducing the satellite defect. Several development experiments including multiple wafer agitation cycles of dynamic puddle, multiple cycles of scanning rinse, pre-wet before development, wafer rotation speed in rinse, wafer rotation speed in drying and advanced defect reduction (ADR) function of track were carried out. The multiple cycles of scanning rinse coupling with the optimal wafer rotation speed of rinse effectively suppresses the count of satellite spots. Pre spin dry in advance of the deionized water (DIW) rinse to minimize the pH shock is also effective to reduce the defect count. Multiple cycles of development puddle and scanning rinse have a synergy effect to lower defectivity up to complete suppression of satellite defect. To minimize the throughput loss induced by the long development time, ADR is proposed as better candidate for fully eliminating the satellite defect.

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