Improved sensing performance, larger pH sensitivity that breaches the Nernst response limit with excellent stability, was realized on polycrystalline silicon based dual-gate (DG) ion-sensitive field-effect transistors. The capacitive coupling between the top and bottom gate oxides for a DG operation amplified its sensitivity to as high as 325.8 mV/pH. In particular, the SiO2/HfO2/Al2O3 (OHA) layer, proposed as an engineered sensing membrane, significantly reinforced the sensing margin of devices as well as the chemical stability for long-term use. The sensing characteristics of the OHA and conventional SiO2 layer were evaluated for single gate and DG operation modes, respectively.

High performance silicon nanowire (SiNW) sensors with SiO2/HfO2/Al2O3 (OHA) engineered sensing thin films were fabricated. A lower interface state density, a larger capacitance and a stronger chemical immunity, which are essential for enhancing the performance of devices, were accomplished by stacking thin SiO2, HfO2, and Al2O3 layers, respectively, in sequence on the SiNW channel. Compared with the conventional single SiO2 thin film, the staked OHA thin films demonstrated improved sensing performances; a higher sensitivity, a lower hysteresis voltage, and a smaller drift rate, as well as a higher output current. Therefore, the SiNW sensors with OHA stacked sensing thin films are very promising to biological and chemical sensor applications.

High performance graphene field-effect transistors (FETs) with a solution-processed Al2O3 sensing membrane were fabricated. The solution-processed deposition technique offers a lot of advantages in terms of low cost, simplicity, high throughput, and large-area devices. Especially, the solution-deposition process is well-suited for membrane formation of graphene FETs, which is vulnerable to plasma or thermal processes for insulator growth on surface. The graphene FETs with a solution-deposited Al2O3 sensing membrane exhibited a higher pH sensitivity as well as good chemical stability. Therefore, the graphene FETs with solution-deposited Al2O3 sensing membrane are very promising to biological sensors application.

CMOS and tunneling FETs (TFETs) utilizing Ge-On-Insulator (GOI) channels on Si substrates are expected as the promising device options for low-power integrated systems. In this paper, we present viable device and process technologies of GOI MOSFETs and TFETs on the Si CMOS platform. High compressive strain, favorable in p-MOSFET applications, is introduced in GOI films by optimizing the Ge condensation process and initial substrate structures, which is one of the most promising technologies to form ultrathin-body GOI p-MOSFETs. Also, source engineering in Ge layers to realize improved tunnel junctions with steep impurity profiles is developed for Ge/GOI TFET applications. In addition, impacts of Ge-based type-II hetero-structures such as Ge/strained-Si and Ge/ZnO on the TFET performance are studied. The electrical characteristics of GOI MOSFETs and TFETs are presented and analyzed from the viewpoints of applied strain, source junction properties and device structures.

The critical issues, technical challenges and viable technologies of tunneling FETs (TFET) using III-V semiconductors and Ge are addressed in this paper. Device engineering indispensable in improving the performance of TFETs is summarized with emphasis on the source junction formation technology. The fabrication and the electrical characteristics of TFETs using InGaAs bulk and quantum well (QW) homo-junctions, GaAsSb/InGaAs type-II hetero-junctions, Ge homo junctions and Ge/strained SOI type-II hetero-junction are presented as viable examples.