Experimental evidence of the optimized interface engineering effects in MoS2 transistors is demonstrated. The MoS2/Y2O3/HfO2 stack offers excellent interface control. Results show that HfO2 layer can be scaled down to 9 nm, yet achieving a near-ideal sub-threshold slope (65 mv/dec) and the highest saturation current (526 μA/μm) of any MoS2 transistor reported to date.

Research into the physical properties of MoS 2 and other semiconducting transition metal dichalcogenides [1] (TMDs) has increased considerably in recent years, owing to their potential applications in post-CMOS electronics [2][3][4] , optoelectronics [5][6][7] and valleytronics [8][9][10] . Some of the properties of monolayer MoS 2 that are advantageous for electronic applications include a direct band gap of 1.8 eV [11,12] as well as a film thickness of less than 1 nm which gives superior electrostatic control of the charge density and current even at the transistor scaling limit [3,13] . In spite of these favorable properties, the widely reported low electron mobility in monolayer MoS 2 poses a serious obstacle to its integration into post-CMOS nanoelectronics. The nature of charge transport in MoS 2 , especially at room temperature, remains poorly understood despite considerable amount of theoretical and experimental researches.For example, the theoretically predicted intrinsic phonon-limited mobility at room temperature is in the range of 200-410 cm 2 /Vs [14.15] while most experimentally reported values are much smaller [16][17][18][19][20][21][22][23] . Before any semiconducting material can become useful for potential nanoelectronic device applications, a critical assessment of its intrinsic charge transport properties at room temperature is needed, requiring the realization of high-quality samples with carrier mobility in the phonon-limited regime.The phonon-limited transport regime was demonstrated for graphene [24] and carbon nanotubes [25] . However, despite many recent efforts to improve carrier mobility by means of topgate [17] , chemical functionalization [21] and BN gate dielectrics [22] , phonon-limited transport regime has not been explicitly demonstrated in monolayer TMDs including MoS 2 .The possible reasons for the discrepancy between the theoretical upper limit and experimental data include Coulomb impurities (CI), traps and defects in low-quality samples [19][20][21][22][23] . These extrinsic sources of scattering have so far precluded any rigorous examination of the intrinsic scattering mechanisms that affect electron mobility. A particularly important source of scattering is from CI at the semiconductor-dielectric interface, which is believed to be the most important limiting factor in current MoS 2 devices [26] . Recently, it has been demonstrated that by sandwiching the monolayer MoS 2 channel between BN layers, CI scattering can be significantly suppressed, leading to a record-high mobility of over 1000 cm 2 /Vs at low temperatures [22][23] . The technologically relevant room-temperature mobility, however, still lags the best devices on SiO 2 for reasons not well understood. Nonetheless, significant recent progress in reducing the deleterious effects of CI, traps and defects on the mobility [20][21][22][23] begin to set the stage for the realization of room-temperature charge transport in the phonon-limited regime.It has been shown experimentally that the deposition of a high-κ top ...

No abstract

The combination of high-quality Al2 O3 dielectric and thiol chemistry passivation can effectively reduce the density of interface traps and Coulomb impurities, leading to a significant improvement of the mobility and a transition of the charge transport from the insulating to the metallic regime. A record high mobility of 83 cm(2) V(-1) s(-1) (337 cm(2) V(-1) s(-1) ) is reached at room temperature (low temperature) for monolayer WS2 . A theoretical model for electron transport is also developed.

Graphene is a promising candidate in analog electronics with projected operation frequency well into the terahertz range. In contrast to the intrinsic cutoff frequency (f) of 427 GHz, the maximum oscillation frequency (f) of graphene device still remains at low level, which severely limits its application in radio frequency amplifiers. Here, we develop a novel transfer method for chemical vapor deposition graphene, which can prevent graphene from organic contamination during the fabrication process of the devices. Using a self-aligned gate deposition process, the graphene transistor with 60 nm gate length exhibits a record high f of 106 and 200 GHz before and after de-embedding, respectively. This work defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra high frequency circuits.