Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices

Li, Weisheng; Zhou, Jian; Cai, Songhua; Yu, Zhihao; Zhang, Jialin; Fang, Nan; Li, Taotao; Wu, Yun; Chen, Tangsheng; Xie, Xiaoyu; Ma, Haibo; Yan, Keding; Dai, Ningxuan; Wu, Xiangjin; Zhao, Huijuan; Wang, Zixuan; He, Daowei; Pan, Lijia; Shi, Yi; Wang, Peng; Chen, Wei; Nagashio, Kosuke; Duan, Xiangfeng; Wang, Xinran

doi:10.1038/s41928-019-0334-y

Cited by 292 publications

(257 citation statements)

References 48 publications

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“…1c) is the use of molecular crystal seeding layers (e.g. perylene-tetracarboxylic dianhydride (PTCDA)) when growing oxides using atomic layer deposition (ALD) 39,40 . However, these layers are formed by discrete molecules and thus making homogeneous films may be challenging.…”

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confidence: 99%

“…For defective oxides, trap-assisted tunneling can lead to a significant contribution at low voltages, which is not accounted for in our best-case model. c Experimental gate leakage currents versus EOT measured at standard FET operating gate voltages 1-3 V. Literature data shown with open symbols for Si-based [59][60][61][62] and filled symbols for 2D-based structures 39,40,46,[63][64][65][66] .…”

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confidence: 99%

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Insulators for 2D nanoelectronics: the gap to bridge

et al. 2020

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Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators.

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confidence: 99%

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confidence: 99%

Insulators for 2D nanoelectronics: the gap to bridge

et al. 2020

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“…The 2D nanomaterials have been considered as potential building blocks for a number of electronic and optical components, including nonvolatile memory devices, [ 1,2 ] field‐effect transistors (FETs), [ 3,4 ] photonics devices, and photodetectors. [ 5,6 ] As the most outstanding 2D nanomaterials, graphene exhibits excellent mechanical, electronic, optical, and thermal properties.…”

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confidence: 99%

High‐Performance Broadband Tungsten Disulfide Photodetector Decorated with Indium Arsenide Nanoislands

Yang

Liu

et al. 2020

Physica Status Solidi (a)

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The 2D tungsten disulfide (WS2), as a typical transition metal dichalcogenide (TMD), has aroused intense research interests in photodetection. However, the limited detection wavelength ranges and low photoresponsivity hinder its further application. To promote the application of WS2 in optoelectronics fields, indium arsenide (InAs) nanoislands decorated WS2 are utilized to fabricate photodetectors in this work. Owing to the photogating effect and localized surface plasmon resonance (LSPR), a significant enhancement of photocurrent response (≈1 mA W−1) is obtained by coupling WS2 with InAs nanoislands. Furthermore, the extended detection wavelength up to 1060 nm is realized due to the efficient light absorption in IR range of InAs nanoislands. The high performance, stability, and reliability in ambient temperature strongly indicate that the InAs nanoislands/WS2 heterostructure can be considered as a promising material for TMDs‐based broadband optoelectronic devices in the future.

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“…Zheng et al 22 found the low temperature Al 2 O 3 ALD layer to be low density and have low dielectric constant requiring deposition of a second higher temperature high quality layer. On the other hand, seeding-layers consisting of thin polymers 24 , metal-oxides 25,26 , or metals 27 the graphene surface or inserting a seed layer between graphene and the ALD dielectric can introduce interfacial charges and traps, reduce the total dielectric constant of the gate stack, and limit the minimum equivalent oxide thickness (EOT) 4,22,28 . One alternative is to use a 2D buffer layer on top of the graphene to protect the interface during ALD 29,30 .…”

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Two-dimensional BN buffer for plasma enhanced atomic layer deposition of Al2O3 gate dielectrics on graphene field effect transistors

Snure

Vangala

Prusnick

et al. 2020

Sci Rep

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Here, we investigate the use of few-layer metal organic chemical vapor deposition (MOCVD) grown BN as a two-dimensional buffer layer for plasma enhanced atomic layer deposition (PE-ALD) of Al2O3 on graphene for top gated field effect transistors (FETs). The reactive nature of PE-ALD enables deposition of thin (2 nm) dielectrics directly on graphene and other two-dimensional materials without the need for a seed or functionalization layer; however, this also leads to significant oxidation of the graphene layer as observed by Raman. In FETs, we find this oxidation destroys conductivity in the graphene channel. By transferring thin (1.6 nm) MOCVD BN layers on top of graphene channels prior to PE-ALD, the graphene is protected from oxidation enabling BN/Al2O3 layers as thin as 4 nm. Raman and X-ray photoelectron spectroscopy on BN films show no significant oxidation caused by PE-ALD of Al2O3. Inserting the BN layer creates an atomically abrupt interface significantly reducing interface charges between the graphene and Al2O3 as compared to use of a 2 nm Al buffer layer. This results in a much smaller Dirac voltage (− 1 V) and hysteresis (0.9 V) when compared to FETs with the Al layer (VDirac = − 6.1 V and hysteresis = 2.9 V).

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Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices

Cited by 292 publications

References 48 publications

Insulators for 2D nanoelectronics: the gap to bridge

Insulators for 2D nanoelectronics: the gap to bridge

High‐Performance Broadband Tungsten Disulfide Photodetector Decorated with Indium Arsenide Nanoislands

Two-dimensional BN buffer for plasma enhanced atomic layer deposition of Al2O3 gate dielectrics on graphene field effect transistors

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