This paper presents the device-technological simulation of local 3D SOI structures. These structures are created by use microcavities under surface of silicon wafer. Is shown that proposed microcavities could be use as a constructive material for CMOS transistor array on the bulk silicon and 3D SOI-CMOS transistor array, as well as the sensitive elements and their combinations. Such structures allow creation and monolithic integration the CMOS, SOI-CMOS circuits and sensitive elements for IC and SoC.

Base technology of local 3D SOI-structures formation has been proposed. Using this technology the electrical characteristics were developed and simulated of following original device elements for the microsystem applications: standard and matrix SOI CMOS-transistors with 3D gates, switching elements on Schottky diodes, contact electrodes with 3D surface, elements for highly sensitive integral accelerometers with registration of a field emission current, hermetical microcavities and microchannels under the surface of a SOI-substrate, field emission silicon microcathodes.

The two methods of the formation of the silicon-on-insulator (SOI) local structures have been proposed. The first one is based on the stimulated lateral epitaxial growth and planarization of Si monocrystal film. The second one is based on local thermal oxidation of Si buried layer through horizontal tunnels. The obtained SOIstructures are used in a base matrix crystal fabrication technology for the construction of micro-systems. It is proposed to add to elements of a base crystal of a matrix of cells of field emission micro-cathodes with control circuits. The fabrication technology and the layout of a field emission micro-cathode cell with control high-voltage SOI MOS-transistor has been developed. The computer simulation of high-voltage SOI MOS-transistor static characteristics has been performed.

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