Demands for mobile phones with smaller form factor and lower cost have driven enhanced integration of electronics components. However, surface acoustic wave (SAW) filters must be fabricated on piezoelectric substrates, and so they are difficult to monolithically integrate on semiconductor chips. This paper reports on a compact wafer-scale packaged SAW filter stacked over a transceiver chip in a quad flat-pack no-lead (QFN) package. An integrated passive device (IPD) provided redistribution and matching between the SAW filter output and the transceiver input. Both extended global system for mobile communications (EGSM) and DCS filters were evaluated. Results demonstrated that conventional packaging techniques can be used to successfully assemble stacked SAW on transceiver modules without damage. SAW compact models based on the coupling of modes model were developed to facilitate system design. Electromagnetic simulations of coupling between SAW filters and inductors integrated on the transceiver suggested that design care is needed to avoid interactions, especially if an IPD is not used as a spacer. With appropriate design, stacked SAW filter on transceiver offers viable module integration.Index Terms-Land mobile radio cellular systems, multichip modules, semiconductor device packaging, surface acoustic wave (SAW) filters.

No abstract

RF modules are building blocks for future wireless communication products. A process that combines electromagnetic (EM) simulation with measurement data provides a means to develop circuit simulation libraries for embedded passive components in low temperature cofired ceramic (LTCC) substrates.

No abstract

This paper summarizes a study of chip scale packages (CSP) to determine their maximum allowable power dissipation within typical system level environments. These results can be used to determine the applicability of utilizing CSPs from the standpoint of die power dissipation. Both steady state and transient thermal performance is covered in this study. The steady state portion used in-house software, while closed-form solutions were utilized for the transient analysis. The steady state power limit, while governed by a number of parameters, is dependent mainly upon system level parameters (heatsinking, cooling mode -i.e., natural or forced convection, and PCB power loading). Thermal enhancement features (e.g. thermal vias and bumps) are not generally effective in increasing the maximum power that can be dissipated by the package in the end use environment. The variables investigated in the steady state study included die size, thermal vias and bumps, the addition of a heatsink, natural/forced convection boundary conditions, printed circuit board (PCB) heat loading, and PCB thermal conductivity. The transient portion considered die size, pulse shape and duration, and the addition of a heatsink. For relatively short duration transients (e.g. switching an inductive load), the power limit is governed by the die geometry; magnitude, shape and duration of the heating pulse; and the starting and maximum allowable temperatures of the junction.