No abstract

No abstract

No abstract

A 90 nm generation logic technology with Cu / low-k interconnects is reported. SOnm transistors are employed gate oxide with 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 pA/pm and 360 pA/pm for NMOS and PMOS respectively, while generic transistors have currents of 640 pA/pm and 260 pA/pm respectively. Low power process using high-k gate dielectrics and SO1 process are also provided in this technology. The low-k SiOC material with 2.9 in the.k value is used for 9 layers of dual damascene Cu / low-k interconnects. The effective k (ken) value of interconnect is about 3.6. Fully working 6-T S U M cell with an area of 1.1 pm2 and SNM value of 330mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppmiv.

Electromigration behavior of dual damascene Cu interconnect has been investigated comparing PE-TEOS Si02 with fluorine doped SiOZ(FSG). MTFs of FSG in both line and contact EM tests were significantly shorter than those of PE-TEOS. The higher compressive stress and fluorine of FSG dielectric are considered to affect the EM reliability performance of the confined Cu interconnect.