1AApproved for puh,ic rleas/. AbstractDitx iatf n U ti.ted...The J-Machine s a fine-grain concurrent computer that provides low-overhead jrimitive mechanisms for !ommunication, synchronization, and translation. Communicati )n mechanisms are provided that permit a node to send a message to any other nod in the machine in < 2p s. On message arrival, a task is created and dispatched in < 1 s. A translation mechanism supports a global virtual address space. These mechanisms efficiently support most proposed models of concurrent computation. The hardware is an ensemble of up to 65,536 nodes each containing a 36-bit processor, 4K 36-bit words of memory, and a router. The nodes are connected by a high-speed 3-D mesh network. This design was chosen to make the most efficient use of available chip and board area. AbstractThe J-Machine is a fine-grain concurrent computer that provides low-overhead primitive mechanisms for communication, synchronization, and translation. Communication mechanisms are provided that permit a node to send a message to any other node in the machine in < 2ps. On message arrival, a task is created and dispatched in < ljis. A translation mechanism supports a global virtual address space. These mechanisms efficiently support most proposed nodels of concurrei t computation. The hardware is an ensemble of up to 65,536 nodes each containing a 36-bit processor, 4K 36-bit words of memory, and a router. The nodes are connected by a highspeed 3-D mesh network. This design was chosen to make the most efficient use of available chip and board area.

We propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches. Our architecture also includes a novel memory organization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. Simulation results suggest that this architecture reduces message reception overhead by more than an order of magnitude.

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We propole a machine architecture for a high-performaxe proceuieg node for a mueage-pas&g, MIMD concurrent computer. The principal mee,haaismn for attaining this goal are the direct execution and bufferius of meesylee and a memory-based architecture that permit@ very fast contut witches. Our architecture &o ineluder a aevel msmory orga-nis&x~ that permita both indexed and aeeecikve acceuu and that incorporates sa itwtruction buffer and me-age queer. Simulation re mite suggest that thL architecture reduccl mauge reception overheed by more thau an order of magnitude.

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