Many low-voltage chips such as sensor networks and biomedical applications need large-capacity low-V DDmin -delay-product embedded ROM for storing fixed programs and data [1]. NOR-ROMs provide low V DD and high speed for smallcapacity applications with a short bitline (BL) [2]. However, if read-1 noise can be eliminated, a NAND-ROM is superior [1] for large-capacity storage in standby-dominated low-voltage chips because of smaller area, narrower cell-current (I CELL ) distribution, and lower standby current. Static NAND-ROM with short BL [1] achieves small read-1 noise and low V DD with a 33% area penalty. Applying selected precharge [3], driving source-line (SL) [4], or BL-shield [5], [6] schemes to NAND-ROM can eliminate only one of the read-1 noise sources, which are charge sharing, BL leakage, and BL crosstalk. The remaining read-1 noise reduces the sensing margins for reading 1-cells (V SM1 ) and 0-cells (V SM0 ) and limits the V DDmin and speed of NAND-ROMs. This paper presents dynamic split source-lines (DSSL) scheme to eliminate read-1 noise and a data-aware sensing reference (DASR) scheme to expand V SM0 to tolerate larger I CELL variations for large-capacity low-voltage NAND-ROM. These schemes enable largecapacity NAND-ROM to achieve lower V DDmin , higher speed, and lower power consumption with small area overhead. Figure 14.6.1 shows the structure of the DSSL and conventional metal-code NAND-ROM. The DSSL scheme employs two horizontal split SLs for the NANDchains (NDCs) in the same single sector, rather than a single common SL or vertical split SLs (for different columns [7]) in conventional arrays. Since there are no program and erase operations in a NAND-ROM, each NDC consists of k stacked NMOS bitcells and only one select-gate (SG), rather than the two SGs used in a NAND-Flash. As in conventional NAND-ROMs, all wordlines (WLs) are kept at V DD and all SG-lines (SGLs) are grounded in the precharge phase or standby mode. Unlike connecting to ground in conventional NAND-ROMs, all DSSL SLs are held at V DD . Since all bitcells are on in the precharge phase, all source/drain parasitic capacitors in each NDC are precharged to high, rather than grounded, as in a conventional NAND-ROM. Thus, there are no grounded capacitors to generate a false voltage drop (V BL-CS ) on a precharged BL due to charge sharing in the sensing phase.During sensing, only one SL of the selected sector (STR[p]) is discharged to ground, as Fig. 14.6.2 shows. The grounded SL provides the I CELL to discharge the selected BL for reading a 0-cell during the SG pulse (T SG ). A 1-cell, without a metal code-layer shorting its source and drain, is off (WL= 0) during sensing and its BL remains at V DD . The other SL of the selected sectors in the DSSL array is kept at V DD . If the neighboring bitcells (BC[n-1] and BC[n+1]) are 0-cells, this DSSL scheme does not furnish neighboring NDCs with the driving source required to develop their BL voltage drops onto neighboring BLs (BL[n-1] and BL[n+1]) of the selected BL[n] due to dummy read-0 ope...
