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A B S T R A C T investigated by direct application of moisture on unpassivated M1 and passivated M3 dry-ILD Steam stress was performed on n-and pwafers. EXPERIMENTALMOSFETs of a single-level metal process t o simulate the backend process induced moisture penetration effect and the results of subsequent hot-carrier stresses were then compared with grid--Of-Line (EOL) transistors of a triple-layer metal (MS) CMOS technology with different JnterLayer Dielectric (ILD) processes. Our data showed good correlation between the effect of steam stress on M1 device and the water induced M3 device deterioration. Moisture penetration deteriorates nand pMOSFETs transistor characteristics and hotcarrier performance. The effect of hot-carrier moisture induced degradation is more severe on nMOSFETs. I N T R O D U C T I O N Moisture diffusion occurs during spin-on-glass (SOG), Tetraethyl orthosilicate (TEOS), and TEOS/O, ILD processing [I-51 and results in oxide and hot-carrier performance degradation. Extensive work to evaluate the mechanisms 'for the moisture effect and methods t o reduce t h e hot-carrier degradation have been published [l-41; most of the previous studies were concentrated on moisture effects of n-MOSFETs, while the effect of moisture on pMOSFETs IS] were seldom mentioned. It isreasonable to assume that there should be no difference in moisture effects between n-and pMOSFETs because the gate oxide for n-and pMOSFETs are degraded similarly. In this paper, we will explain t h e difference in hot-carrier moisture sensitivity between n-and pMOSFETs.In this study, the moisture-rich ILD (wet-ILD) and the reduced-moisture ILD (dry-ILD) processes were utilized to qualitatively compare the effect of moisture on the n-and p-MOSFETs device characteristics a n d reliability.T h e passivated EOL MS transistors with wet-ILD exhibited wide scatter in transistor parameters such as .gm, V,, and drain saturation current Idlat, while devices processed through the first metal layer (Ml) without the ILD process had tight device characteristics. The wet-ILD MS transistors also showed significantly more bias-temperature degradation than the M1 or EOL MS dry-ILD process. The hot-carrier performance of transistors of the M1 process are equivalent to that of the EOL MS dry-ILD CMOS process, proving that moisture alone is the main source for the MS wet-ILD device degradation. The claim was further 0-7803-1450-6 $3.00 0 1993 IEEE I I I -The devices studied were fabricated using a 0.8pm CMOS technology with 15 nm gate oxide, complementary TiSi2-coated poly gate, Lightlydoped-drain (LDD) structures, and triple level metal process. Two ILD processes with different water c o n t e n t s were chosen.Q u a n t i t a t i v e meaaurement of moisture content were obtained by exposing the ILD films to equilibrate with ambient air for few days and then integrating the amount of water that outgassed during heating to 40OoC. The ratio of the water content of wet-ILD to dry-ILD prdcesses was about S0:l.Two bypes of moisture stresses, steam and HAST, we...

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Via delamination, a novel electromigration failure mechanism, has been investigated and understood. The mass transport model, in conjunction with environmental, thermal, and mechanical stresses was proposed to explain this failure mechanism. Process enhancements, which include lowering the thin film stresses and strengthening the adhesion between the tungsten plug/metal stack and metalhnter-level dielectric interfaces, have effectively eliminated this reliability failure mode.

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